Commit db865ee4 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom',... 

Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next

 - Support for Xilinx Versal platform clks
 - Display clk controller on qcom sc7180
 - Video clk controller on qcom sc7180
 - Graphics clk controller on qcom sc7180
 - CPU PLLs for qcom msm8916
 - Fixes for clk controllers on qcom msm8998 SoCs
 - Move qcom msm8974 gfx3d clk to RPM control
 - Display port clk support on qcom sdm845 SoCs
 - Global clk controller on qcom ipq6018
 - Adjust composite clk to new way of describing clk parents
 - Add a driver for BCLK of Freescale SAI cores

* clk-imx: (32 commits)
  clk: imx: Add support for i.MX8MP clock driver
  dt-bindings: imx: Add clock binding doc for i.MX8MP
  clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
  clk: imx: imx8mq: Switch to clk_hw based API
  clk: imx: imx8mm: Switch to clk_hw based API
  clk: imx: imx8mn: Switch to clk_hw based API
  clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
  clk: imx: gate3: Switch to clk_hw based API
  clk: imx: add hw API imx_clk_hw_mux2_flags
  clk: imx: add imx_unregister_hw_clocks
  clk: imx: clk-composite-8m: Switch to clk_hw based API
  clk: imx: clk-pll14xx: Switch to clk_hw based API
  clk: imx7up: Rename the clks to hws
  clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
  clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
  clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
  clk: imx: Rename sccg and frac pll register to suggest clk_hw
  clk: imx: imx7ulp composite: Rename to show is clk_hw based
  clk: imx: pllv2: Switch to clk_hw based API
  clk: imx: pllv1: Switch to clk_hw based API
  ...

* clk-ti:
  clk: ti: clkctrl: Fix hidden dependency to node name
  clk: ti: add clkctrl data dra7 sgx
  clk: ti: omap5: Add missing AESS clock
  clk: ti: dra7: fix parent for gmac_clkctrl
  clk: ti: dra7: add vpe clkctrl data
  clk: ti: dra7: add cam clkctrl data
  dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock

* clk-xilinx:
  clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
  clk: zynqmp: Fix divider calculation
  clk: zynqmp: Add support for get max divider
  clk: zynqmp: Warn user if clock user are more than allowed
  clk: zynqmp: Extend driver for versal
  dt-bindings: clock: Add bindings for versal clock driver

* clk-nvidia:
  clk: tegra20/30: Explicitly set parent clock for Video Decoder
  clk: tegra20/30: Don't pre-initialize displays parent clock
  clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
  clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
  clk: tegra: Mark fuse clock as critical

* clk-qcom: (35 commits)
  clk: qcom: rpmh: Sort OF match table
  dt-bindings: fix warnings in validation of qcom,gcc.yaml
  dt-binding: fix compilation error of the example in qcom,gcc.yaml
  clk: qcom: Add ipq6018 Global Clock Controller support
  clk: qcom: Add DT bindings for ipq6018 gcc clock controller
  clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks
  clk: qcom: rpmh: Add IPA clock for SC7180
  clk: qcom: rpmh: skip undefined clocks when registering
  clk: qcom: Add video clock controller driver for SC7180
  dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
  dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
  clk: qcom: Add graphics clock controller driver for SC7180
  dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings
  dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
  clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent
  clk: qcom: Add display clock controller driver for SC7180
  dt-bindings: clock: Introduce QCOM sc7180 display clock bindings
  dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings
  clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration
  clk: qcom: alpha-pll: Remove useless read from set rate
  ...

* clk-freescale:
  clk: fsl-sai: new driver
  dt-bindings: clock: document the fsl-sai driver
  clk: composite: add _register_composite_pdata() variants

* clk-qoriq:
  clk: qoriq: add ls1088a hwaccel clocks support
  clk: ls1028a: Add clock driver for Display output interface
  dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
parents 6e7a9f0c 498e1652 660b94e0 34bbe036 185dfe32 9e0cda72 9cd10205 a932872f

Documentation/devicetree/bindings/clock/fsl,plldig.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding



maintainers:

  - Wen He <wen.he_1@nxp.com>



description: |

  NXP LS1028A has a clock domain PXLCLK0 used for the Display output

  interface in the display core, as implemented in TSMC CLN28HPM PLL.

  which generate and offers pixel clocks to Display.



properties:

  compatible:

    const: fsl,ls1028a-plldig



  reg:

    maxItems: 1



  '#clock-cells':

    const: 0



  fsl,vco-hz:

     description: Optional for VCO frequency of the PLL in Hertz.

        The VCO frequency of this PLL cannot be changed during runtime

        only at startup. Therefore, the output frequencies are very

        limited and might not even closely match the requested frequency.

        To work around this restriction the user may specify its own

        desired VCO frequency for the PLL.

     minimum: 650000000

     maximum: 1300000000

     default: 1188000000



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



examples:

  # Display PIXEL Clock node:

  - |

    dpclk: clock-display@f1f0000 {

        compatible = "fsl,ls1028a-plldig";

        reg = <0x0 0xf1f0000 0x0 0xffff>;

        #clock-cells = <0>;

        clocks = <&osc_27m>;

    };



...

Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/fsl,sai-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale SAI bitclock-as-a-clock binding



maintainers:

  - Michael Walle <michael@walle.cc>



description: |

  It is possible to use the BCLK pin of a SAI module as a generic clock

  output. Some SoC are very constrained in their pin multiplexer

  configuration. Eg. pins can only be changed groups. For example, on the

  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,

  the second pins are wasted. Using this binding it is possible to use the

  clock of the second SAI as a MCLK clock for an audio codec, for example.



  This is a composite of a gated clock and a divider clock.



properties:

  compatible:

    const: fsl,vf610-sai-clock



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 0



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        mclk: clock-mclk@f130080 {

            compatible = "fsl,vf610-sai-clock";

            reg = <0x0 0xf130080 0x0 0x80>;

            #clock-cells = <0>;

            clocks = <&parentclk>;

        };

    };

Documentation/devicetree/bindings/clock/imx8mp-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/imx8mp-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8M Plus Clock Control Module Binding



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  NXP i.MX8M Plus clock control module is an integrated clock controller, which

  generates and supplies to all modules.



properties:

  compatible:

    const: fsl,imx8mp-ccm



  reg:

    maxItems: 1



  clocks:

    items:

      - description: 32k osc

      - description: 24m osc

      - description: ext1 clock input

      - description: ext2 clock input

      - description: ext3 clock input

      - description: ext4 clock input



  clock-names:

    items:

      - const: osc_32k

      - const: osc_24m

      - const: clk_ext1

      - const: clk_ext2

      - const: clk_ext3

      - const: clk_ext4



  '#clock-cells':

    const: 1

    description:

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h

      for the full list of i.MX8M Plus clock IDs.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



examples:

  # Clock Control Module node:

  - |

    clk: clock-controller@30380000 {

        compatible = "fsl,imx8mp-ccm";

        reg = <0x30380000 0x10000>;

        #clock-cells = <1>;

        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,

                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;

        clock-names = "osc_32k", "osc_24m", "clk_ext1",

                      "clk_ext2", "clk_ext3", "clk_ext4";

    };



...

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

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Qualcomm Technologies, Inc. Display Clock Controller Binding

------------------------------------------------------------



Required properties :



- compatible : shall contain "qcom,sdm845-dispcc"

- reg : shall contain base register location and length.

- #clock-cells : from common clock binding, shall contain 1.

- #reset-cells : from common reset binding, shall contain 1.

- #power-domain-cells : from generic power domain binding, shall contain 1.



Example:

	dispcc: clock-controller@af00000 {

		compatible = "qcom,sdm845-dispcc";

		reg = <0xaf00000 0x100000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		#power-domain-cells = <1>;

	};

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock & Reset Controller Binding



maintainers:

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm display clock control module which supports the clocks, resets and

  power domains.



properties:

  compatible:

    enum:

      - qcom,sc7180-dispcc

      - qcom,sdm845-dispcc



  clocks:

    minItems: 1

    maxItems: 2

    items:

      - description: Board XO source

      - description: GPLL0 source from GCC



  clock-names:

    items:

      - const: xo

      - const: gpll0



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



examples:

  # Example of DISPCC with clock node properties for SDM845:

  - |

    clock-controller@af00000 {

      compatible = "qcom,sdm845-dispcc";

      reg = <0xaf00000 0x10000>;

      clocks = <&rpmhcc 0>, <&gcc 24>;

      clock-names = "xo", "gpll0";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

     };

...