Commit d75c26a9 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-rockchip', 'clk-ingenic', 'clk-bindings', 'clk-samsung'... 

Merge branches 'clk-rockchip', 'clk-ingenic', 'clk-bindings', 'clk-samsung' and 'clk-stm' into clk-next

 - Mark some clks critical on Ingenic X1000
 - Add STM32MP13 RCC driver (Reset Clock Controller)

* clk-rockchip:
  dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML
  dt-bindings: clock: convert rockchip,px30-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML
  dt-binding: clock: Add missing rk3568 cru bindings
  clk: rockchip: Mark hclk_vo as critical on rk3568
  dt-bindings: clock: fix rk3399 cru clock issues
  dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml
  dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml
  dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml

* clk-ingenic:
  clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs
  mips: ingenic: Do not manually reference the CPU clock
  clk: ingenic: Mark critical clocks in Ingenic SoCs
  clk: ingenic: Allow specifying common clock flags

* clk-bindings:
  dt-bindings: clock: Replace common binding with link to schema

* clk-samsung:
  dt-bindings: clock: exynosautov9: correct count of NR_CLK
  clk: samsung: exynosautov9: add cmu_peric1 clock support
  clk: samsung: exynosautov9: add cmu_peric0 clock support
  clk: samsung: exynosautov9: add cmu_fsys2 clock support
  clk: samsung: exynosautov9: add cmu_busmc clock support
  clk: samsung: exynosautov9: add cmu_peris clock support
  clk: samsung: exynosautov9: add cmu_core clock support
  clk: samsung: add top clock support for Exynos Auto v9 SoC
  dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings
  dt-bindings: clock: add clock binding definitions for Exynos Auto v9

* clk-stm:
  clk: stm32mp13: add safe mux management
  clk: stm32mp13: add multi mux function
  clk: stm32mp13: add all STM32MP13 kernel clocks
  clk: stm32mp13: add all STM32MP13 peripheral clocks
  clk: stm32mp13: manage secured clocks
  clk: stm32mp13: add composite clock
  clk: stm32mp13: add stm32 divider clock
  clk: stm32mp13: add stm32_gate management
  clk: stm32mp13: add stm32_mux clock management
  clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
  dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
parents d3d88716 7337342b e98839fb f538ce11 538101dd 83ce0357

Documentation/devicetree/bindings/clock/clock-bindings.txt

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Original line number Diff line number Diff line 
This binding is a work-in-progress, and are based on some experimental

work by benh[1].



Sources of clock signal can be represented by any node in the device

tree.  Those nodes are designated as clock providers.  Clock consumer

nodes use a phandle and clock specifier pair to connect clock provider

outputs to clock inputs.  Similar to the gpio specifiers, a clock

specifier is an array of zero, one or more cells identifying the clock

output on a device.  The length of a clock specifier is defined by the

value of a #clock-cells property in the clock provider node.



[1] https://patchwork.ozlabs.org/patch/31551/



==Clock providers==



Required properties:

#clock-cells:	   Number of cells in a clock specifier; Typically 0 for nodes

		   with a single clock output and 1 for nodes with multiple

		   clock outputs.



Optional properties:

clock-output-names: Recommended to be a list of strings of clock output signal

		    names indexed by the first cell in the clock specifier.

		    However, the meaning of clock-output-names is domain

		    specific to the clock provider, and is only provided to

		    encourage using the same meaning for the majority of clock

		    providers.  This format may not work for clock providers

		    using a complex clock specifier format.  In those cases it

		    is recommended to omit this property and create a binding

		    specific names property.



		    Clock consumer nodes must never directly reference

		    the provider's clock-output-names property.



For example:



    oscillator {

        #clock-cells = <1>;

        clock-output-names = "ckil", "ckih";

    };



- this node defines a device with two clock outputs, the first named

  "ckil" and the second named "ckih".  Consumer nodes always reference

  clocks by index. The names should reflect the clock output signal

  names for the device.



clock-indices:	   If the identifying number for the clocks in the node

		   is not linear from zero, then this allows the mapping of

		   identifiers into the clock-output-names array.



For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:



	oscillator {

		compatible = "myclocktype";

		#clock-cells = <1>;

		clock-indices = <1>, <3>;

		clock-output-names = "clka", "clkb";

	}



	This ensures we do not have any empty strings in clock-output-names





==Clock consumers==



Required properties:

clocks:		List of phandle and clock specifier pairs, one pair

		for each clock input to the device.  Note: if the

		clock provider specifies '0' for #clock-cells, then

		only the phandle portion of the pair will appear.



Optional properties:

clock-names:	List of clock input name strings sorted in the same

		order as the clocks property.  Consumers drivers

		will use clock-names to match clock input names

		with clocks specifiers.

clock-ranges:	Empty property indicating that child nodes can inherit named

		clocks from this node. Useful for bus nodes to provide a

		clock to their children.



For example:



    device {

        clocks = <&osc 1>, <&ref 0>;

        clock-names = "baud", "register";

    };





This represents a device with two clock inputs, named "baud" and "register".

The baud clock is connected to output 1 of the &osc device, and the register

clock is connected to output 0 of the &ref.



==Example==



    /* external oscillator */

    osc: oscillator {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency  = <32678>;

        clock-output-names = "osc";

    };



    /* phase-locked-loop device, generates a higher frequency clock

     * from the external oscillator reference */

    pll: pll@4c000 {

        compatible = "vendor,some-pll-interface"

        #clock-cells = <1>;

        clocks = <&osc 0>;

        clock-names = "ref";

        reg = <0x4c000 0x1000>;

        clock-output-names = "pll", "pll-switched";

    };



    /* UART, using the low frequency oscillator for the baud clock,

     * and the high frequency switched PLL output for register

     * clocking */

    uart@a000 {

        compatible = "fsl,imx-uart";

        reg = <0xa000 0x1000>;

        interrupts = <33>;

        clocks = <&osc 0>, <&pll 1>;

        clock-names = "baud", "register";

    };



This DT fragment defines three devices: an external oscillator to provide a

low-frequency reference clock, a PLL device to generate a higher frequency

clock signal, and a UART.



* The oscillator is fixed-frequency, and provides one clock output, named "osc".

* The PLL is both a clock provider and a clock consumer. It uses the clock

  signal generated by the external oscillator, and provides two output signals

  ("pll" and "pll-switched").

* The UART has its baud clock connected the external oscillator and its

  register clock connected to the PLL clock (the "pll-switched" signal)



==Assigned clock parents and rates==



Some platforms may require initial configuration of default parent clocks

and clock frequencies. Such a configuration can be specified in a device tree

node through assigned-clocks, assigned-clock-parents and assigned-clock-rates

properties. The assigned-clock-parents property should contain a list of parent

clocks in the form of a phandle and clock specifier pair and the

assigned-clock-rates property should contain a list of frequencies in Hz. Both

these properties should correspond to the clocks listed in the assigned-clocks

property.



To skip setting parent or rate of a clock its corresponding entry should be

set to 0, or can be omitted if it is not followed by any non-zero entry.



    uart@a000 {

        compatible = "fsl,imx-uart";

        reg = <0xa000 0x1000>;

        ...

        clocks = <&osc 0>, <&pll 1>;

        clock-names = "baud", "register";



        assigned-clocks = <&clkcon 0>, <&pll 2>;

        assigned-clock-parents = <&pll 2>;

        assigned-clock-rates = <0>, <460800>;

    };



In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and

the <&pll 2> clock is assigned a frequency value of 460800 Hz.



Configuring a clock's parent and rate through the device node that consumes

the clock can be done only for clocks that have a single user. Specifying

conflicting parent or rate configuration in multiple consumer nodes for

a shared clock is forbidden.



Configuration of common clocks, which affect multiple consumer devices can

be similarly specified in the clock provider node.



==Protected clocks==



Some platforms or firmwares may not fully expose all the clocks to the OS, such

as in situations where those clks are used by drivers running in ARM secure

execution levels. Such a configuration can be specified in device tree with the

protected-clocks property in the form of a clock specifier list. This property should

only be specified in the node that is providing the clocks being protected:



   clock-controller@a000f000 {

        compatible = "vendor,clk95;

        reg = <0xa000f000 0x1000>

        #clocks-cells = <1>;

        ...

        protected-clocks = <UART3_CLK>, <SPI5_CLK>;

   };
 
This file has moved to the clock binding schema:

https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt

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* Rockchip PX30 Clock and Reset Unit



The PX30 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"

- compatible: CRU should be "rockchip,px30-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- clocks: A list of phandle + clock-specifier pairs for the clocks listed

          in clock-names

- clock-names: Should contain the following:

  - "xin24m" for both PMUCRU and CRU

  - "gpll" for CRU (sourced from PMUCRU)

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing, pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "i2sx_clkin" - external I2S clock - optional,

 - "gmac_clkin" - external GMAC clock - optional



Example: Clock controller node:



	pmucru: clock-controller@ff2bc000 {

		compatible = "rockchip,px30-pmucru";

		reg = <0x0 0xff2bc000 0x0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	cru: clock-controller@ff2b0000 {

		compatible = "rockchip,px30-cru";

		reg = <0x0 0xff2b0000 0x0 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@ff030000 {

		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff030000 0x0 0x100>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;

		clock-names = "baudclk", "apb_pclk";

		reg-shift = <2>;

		reg-io-width = <4>;

	};

Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip PX30 Clock and Reset Unit (CRU)



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The PX30 clock controller generates and supplies clocks to various

  controllers within the SoC and also implements a reset controller for SoC

  peripherals.

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clocks are defined as

  preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be

  used in device tree sources. Similar macros exist for the reset sources in

  these files.

  There are several clocks that are generated outside the SoC. It is expected

  that they are defined using standard clock bindings with following

  clock-output-names:

    - "xin24m"     - crystal input       - required

    - "xin32k"     - rtc clock           - optional

    - "i2sx_clkin" - external I2S clock  - optional

    - "gmac_clkin" - external GMAC clock - optional



properties:

  compatible:

    enum:

      - rockchip,px30-cru

      - rockchip,px30-pmucru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 1

    items:

      - description: Clock for both PMUCRU and CRU

      - description: Clock for CRU (sourced from PMUCRU)



  clock-names:

    minItems: 1

    items:

      - const: xin24m

      - const: gpll



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the "general register files" (GRF),

      if missing pll rates are not changeable, due to the missing pll

      lock status.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"

  - "#reset-cells"



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: rockchip,px30-cru



    then:

      properties:

        clocks:

          minItems: 2



        clock-names:

          minItems: 2



    else:

      properties:

        clocks:

          maxItems: 1



        clock-names:

          maxItems: 1



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/px30-cru.h>



    pmucru: clock-controller@ff2bc000 {

      compatible = "rockchip,px30-pmucru";

      reg = <0xff2bc000 0x1000>;

      clocks = <&xin24m>;

      clock-names = "xin24m";

      rockchip,grf = <&grf>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };



    cru: clock-controller@ff2b0000 {

      compatible = "rockchip,px30-cru";

      reg = <0xff2b0000 0x1000>;

      clocks = <&xin24m>, <&pmucru PLL_GPLL>;

      clock-names = "xin24m", "gpll";

      rockchip,grf = <&grf>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

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* Rockchip RK3036 Clock and Reset Unit



The RK3036 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: should be "rockchip,rk3036-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "ext_i2s" - external I2S clock - optional,

 - "rmii_clkin" - external EMAC clock - optional



Example: Clock controller node:



	cru: cru@20000000 {

		compatible = "rockchip,rk3036-cru";

		reg = <0x20000000 0x1000>;

		rockchip,grf = <&grf>;



		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@20060000 {

		compatible = "snps,dw-apb-uart";

		reg = <0x20060000 0x100>;

		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

		clocks = <&cru SCLK_UART0>;

	};

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3036 Clock and Reset Unit (CRU)



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The RK3036 clock controller generates and supplies clocks to various

  controllers within the SoC and also implements a reset controller for SoC

  peripherals.

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clocks are defined as

  preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be

  used in device tree sources. Similar macros exist for the reset sources in

  these files.

  There are several clocks that are generated outside the SoC. It is expected

  that they are defined using standard clock bindings with following

  clock-output-names:

    - "xin24m"     - crystal input       - required

    - "ext_i2s"    - external I2S clock  - optional

    - "rmii_clkin" - external EMAC clock - optional



properties:

  compatible:

    enum:

      - rockchip,rk3036-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    maxItems: 1



  clock-names:

    const: xin24m



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the "general register files" (GRF),

      if missing pll rates are not changeable, due to the missing pll

      lock status.



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    cru: clock-controller@20000000 {

      compatible = "rockchip,rk3036-cru";

      reg = <0x20000000 0x1000>;

      rockchip,grf = <&grf>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };