Commit 7337342b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v5.19-rockchip-clk2' of... 

Merge tag 'v5.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

Conversion from txt to Yaml for a number of Rockchip
clock bindings.

Some fixes for recent yaml conversion of clock bindinds
and making the hclk_vo critical for rk3568.

* tag 'v5.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML
  dt-bindings: clock: convert rockchip,px30-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML
  dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML
  dt-binding: clock: Add missing rk3568 cru bindings
  clk: rockchip: Mark hclk_vo as critical on rk3568
  dt-bindings: clock: fix rk3399 cru clock issues
  dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml
  dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml
  dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml
parents 31231092 32a214cd

Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt

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* Rockchip PX30 Clock and Reset Unit



The PX30 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"

- compatible: CRU should be "rockchip,px30-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- clocks: A list of phandle + clock-specifier pairs for the clocks listed

          in clock-names

- clock-names: Should contain the following:

  - "xin24m" for both PMUCRU and CRU

  - "gpll" for CRU (sourced from PMUCRU)

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing, pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "i2sx_clkin" - external I2S clock - optional,

 - "gmac_clkin" - external GMAC clock - optional



Example: Clock controller node:



	pmucru: clock-controller@ff2bc000 {

		compatible = "rockchip,px30-pmucru";

		reg = <0x0 0xff2bc000 0x0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	cru: clock-controller@ff2b0000 {

		compatible = "rockchip,px30-cru";

		reg = <0x0 0xff2b0000 0x0 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@ff030000 {

		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff030000 0x0 0x100>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;

		clock-names = "baudclk", "apb_pclk";

		reg-shift = <2>;

		reg-io-width = <4>;

	};

Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip PX30 Clock and Reset Unit (CRU)



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The PX30 clock controller generates and supplies clocks to various

  controllers within the SoC and also implements a reset controller for SoC

  peripherals.

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clocks are defined as

  preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be

  used in device tree sources. Similar macros exist for the reset sources in

  these files.

  There are several clocks that are generated outside the SoC. It is expected

  that they are defined using standard clock bindings with following

  clock-output-names:

    - "xin24m"     - crystal input       - required

    - "xin32k"     - rtc clock           - optional

    - "i2sx_clkin" - external I2S clock  - optional

    - "gmac_clkin" - external GMAC clock - optional



properties:

  compatible:

    enum:

      - rockchip,px30-cru

      - rockchip,px30-pmucru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 1

    items:

      - description: Clock for both PMUCRU and CRU

      - description: Clock for CRU (sourced from PMUCRU)



  clock-names:

    minItems: 1

    items:

      - const: xin24m

      - const: gpll



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the "general register files" (GRF),

      if missing pll rates are not changeable, due to the missing pll

      lock status.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"

  - "#reset-cells"



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: rockchip,px30-cru



    then:

      properties:

        clocks:

          minItems: 2



        clock-names:

          minItems: 2



    else:

      properties:

        clocks:

          maxItems: 1



        clock-names:

          maxItems: 1



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/px30-cru.h>



    pmucru: clock-controller@ff2bc000 {

      compatible = "rockchip,px30-pmucru";

      reg = <0xff2bc000 0x1000>;

      clocks = <&xin24m>;

      clock-names = "xin24m";

      rockchip,grf = <&grf>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };



    cru: clock-controller@ff2b0000 {

      compatible = "rockchip,px30-cru";

      reg = <0xff2b0000 0x1000>;

      clocks = <&xin24m>, <&pmucru PLL_GPLL>;

      clock-names = "xin24m", "gpll";

      rockchip,grf = <&grf>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

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* Rockchip RK3036 Clock and Reset Unit



The RK3036 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: should be "rockchip,rk3036-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "ext_i2s" - external I2S clock - optional,

 - "rmii_clkin" - external EMAC clock - optional



Example: Clock controller node:



	cru: cru@20000000 {

		compatible = "rockchip,rk3036-cru";

		reg = <0x20000000 0x1000>;

		rockchip,grf = <&grf>;



		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@20060000 {

		compatible = "snps,dw-apb-uart";

		reg = <0x20060000 0x100>;

		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

		clocks = <&cru SCLK_UART0>;

	};

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3036 Clock and Reset Unit (CRU)



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The RK3036 clock controller generates and supplies clocks to various

  controllers within the SoC and also implements a reset controller for SoC

  peripherals.

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clocks are defined as

  preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be

  used in device tree sources. Similar macros exist for the reset sources in

  these files.

  There are several clocks that are generated outside the SoC. It is expected

  that they are defined using standard clock bindings with following

  clock-output-names:

    - "xin24m"     - crystal input       - required

    - "ext_i2s"    - external I2S clock  - optional

    - "rmii_clkin" - external EMAC clock - optional



properties:

  compatible:

    enum:

      - rockchip,rk3036-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    maxItems: 1



  clock-names:

    const: xin24m



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the "general register files" (GRF),

      if missing pll rates are not changeable, due to the missing pll

      lock status.



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    cru: clock-controller@20000000 {

      compatible = "rockchip,rk3036-cru";

      reg = <0x20000000 0x1000>;

      rockchip,grf = <&grf>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt

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* Rockchip RK3188/RK3066 Clock and Reset Unit



The RK3188/RK3066 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or

			"rockchip,rk3066a-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3188-cru.h and

dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.

Similar macros exist for the reset sources in these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "xin27m" - 27mhz crystal input on rk3066 - optional,

 - "ext_hsadc" - external HSADC clock - optional,

 - "ext_cif0" - external camera clock - optional,

 - "ext_rmii" - external RMII clock - optional,

 - "ext_jtag" - externalJTAG clock - optional



Example: Clock controller node:



	cru: cru@20000000 {

		compatible = "rockchip,rk3188-cru";

		reg = <0x20000000 0x1000>;

		rockchip,grf = <&grf>;



		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@10124000 {

		compatible = "snps,dw-apb-uart";

		reg = <0x10124000 0x400>;

		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <1>;

		clocks = <&cru SCLK_UART0>;

	};