Commit d3d88716 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and 'clk-imx' into clk-next 

 - Convert ux500 to clk_hw
 - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
 - MediaTek MT8186 SoC clk support
 - Move MediaTek driver to clk_hw provider APIs

* clk-ux500:
  clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base()
  clk: ux500: Implement the missing CLKOUT clocks
  clk: ux500: Rewrite PRCMU clocks to use clk_hw_*
  clk: ux500: Drop .is_prepared state from PRCMU clocks
  clk: ux500: Drop .is_enabled state from PRCMU clocks
  dt-bindings: clock: u8500: Add clkout clock bindings

* clk-mtk: (22 commits)
  clk: mediatek: mt8173: Switch to clk_hw provider APIs
  clk: mediatek: Switch to clk_hw provider APIs
  clk: mediatek: Replace 'struct clk' with 'struct clk_hw'
  clk: mediatek: apmixed: Drop error message from clk_register() failure
  clk: mediatek: Make mtk_clk_register_composite() static
  clk: mediatek: use en_mask as a pure div_en_mask
  clk: mediatek: update compatible string for MT7986 ethsys
  clk: mediatek: Add MT8186 ipesys clock support
  clk: mediatek: Add MT8186 mdpsys clock support
  clk: mediatek: Add MT8186 camsys clock support
  clk: mediatek: Add MT8186 vencsys clock support
  clk: mediatek: Add MT8186 vdecsys clock support
  clk: mediatek: Add MT8186 imgsys clock support
  clk: mediatek: Add MT8186 wpesys clock support
  clk: mediatek: Add MT8186 mmsys clock support
  clk: mediatek: Add MT8186 mfgsys clock support
  clk: mediatek: Add MT8186 imp i2c wrapper clock support
  clk: mediatek: Add MT8186 apmixedsys clock support
  clk: mediatek: Add MT8186 infrastructure clock support
  clk: mediatek: Add MT8186 topckgen clock support
  ...

* clk-tegra:
  clk: tegra: Update kerneldoc to match prototypes
  clk: tegra: Replace .round_rate() with .determine_rate()
  clk: tegra: Register clocks from root to leaf
  clk: tegra: Add missing reset deassertion

* clk-allwinner:
  clk: sunxi-ng: h616: Add PLL derived 32KHz clock
  clk: sunxi-ng: h6-r: Add RTC gate clock

* clk-imx:
  clk: imx8mp: fix usb_root_clk parent
  clk: imx8mp: add clkout1/2 support
  clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
  clk: imx8mp: Add DISP2 pixel clock
  clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu()
  clk: imx: Add check for kcalloc
  clk: imx8mn: add GPT support
  dt-bindings: imx: add clock bindings for i.MX8MN GPT
  clk: imx: Remove the snvs clock
  clk: imx8m: check mcore_booted before register clk
  clk: imx: add mcore_booted module paratemter
  clk: imx8mq: add 27m phy pll ref clock
parents 2c29798c bea0b66e 5876ee75 8b9d9e9f 0594058b 3972b152

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml

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+56 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek Functional Clock Controller for MT8186



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description: |

  The clock architecture in MediaTek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The devices provide clock gate control in different IP blocks.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8186-imp_iic_wrap

          - mediatek,mt8186-mfgsys

          - mediatek,mt8186-wpesys

          - mediatek,mt8186-imgsys1

          - mediatek,mt8186-imgsys2

          - mediatek,mt8186-vdecsys

          - mediatek,mt8186-vencsys

          - mediatek,mt8186-camsys

          - mediatek,mt8186-camsys_rawa

          - mediatek,mt8186-camsys_rawb

          - mediatek,mt8186-mdpsys

          - mediatek,mt8186-ipesys

  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    imp_iic_wrap: clock-controller@11017000 {

        compatible = "mediatek,mt8186-imp_iic_wrap";

        reg = <0x11017000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml

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+54 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek System Clock Controller for MT8186



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description: |

  The clock architecture in MediaTek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The apmixedsys provides most of PLLs which generated from SoC 26m.

  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.

  The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.

  The mcusys provides mux control to select the clock source in AP MCU.

  The device nodes also provide the system control capacity for configuration.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8186-mcusys

          - mediatek,mt8186-topckgen

          - mediatek,mt8186-infracfg_ao

          - mediatek,mt8186-apmixedsys

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    topckgen: syscon@10000000 {

        compatible = "mediatek,mt8186-topckgen", "syscon";

        reg = <0x10000000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml

+57 −0
Original line number Diff line number Diff line
@@ -109,6 +109,25 @@ properties: 


    additionalProperties: false



  clkout-clock:

    description: A subnode with three clock cells for externally routed clocks,

      output clocks. These are two PRCMU-internal clocks that can be divided and

      muxed out on the pads of the DB8500 SoC.

    type: object



    properties:

      '#clock-cells':

        description:

          The first cell indicates which output clock we are using,

          possible values are 0 (CLKOUT1) and 1 (CLKOUT2).

          The second cell indicates which clock we want to use as source,

          possible values are 0 thru 7, see the defines for the different

          source clocks.

          The third cell is a divider, legal values are 1 thru 63.

        const: 3



    additionalProperties: false



required:

  - compatible

  - reg
@@ -119,3 +138,41 @@ required: 
  - smp-twd-clock



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/ste-db8500-clkout.h>

    clocks@8012 {

      compatible = "stericsson,u8500-clks";

      reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,

            <0x8000f000 0x1000>, <0xa03ff000 0x1000>,

            <0xa03cf000 0x1000>;



      prcmu_clk: prcmu-clock {

        #clock-cells = <1>;

      };



      prcc_pclk: prcc-periph-clock {

        #clock-cells = <2>;

      };



      prcc_kclk: prcc-kernel-clock {

        #clock-cells = <2>;

      };



      prcc_reset: prcc-reset-controller {

        #reset-cells = <2>;

      };



      rtc_clk: rtc32k-clock {

        #clock-cells = <0>;

      };



      smp_twd_clk: smp-twd-clock {

        #clock-cells = <0>;

      };



      clkout_clk: clkout-clock {

        #clock-cells = <3>;

      };

    };

drivers/clk/imx/clk-composite-8m.c

+11 −8
Original line number Diff line number Diff line
@@ -178,7 +178,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, 
					unsigned long flags)

{

	struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;

	struct clk_hw *div_hw, *gate_hw;

	struct clk_hw *div_hw, *gate_hw = NULL;

	struct clk_divider *div = NULL;

	struct clk_gate *gate = NULL;

	struct clk_mux *mux = NULL;
@@ -223,6 +223,8 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, 
	div->lock = &imx_ccm_lock;

	div->flags = CLK_DIVIDER_ROUND_CLOSEST;



	/* skip registering the gate ops if M4 is enabled */

	if (!mcore_booted) {

		gate = kzalloc(sizeof(*gate), GFP_KERNEL);

		if (!gate)

			goto fail;
@@ -231,6 +233,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, 
		gate->reg = reg;

		gate->bit_idx = PCG_CGC_SHIFT;

		gate->lock = &imx_ccm_lock;

	}



	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

			mux_hw, mux_ops, div_hw,

drivers/clk/imx/clk-imx7d.c

+0 −1
Original line number Diff line number Diff line
@@ -782,7 +782,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) 
	hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);

	hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);

	hws[IMX7D_OCOTP_CLK] = imx_clk_hw_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);

	hws[IMX7D_SNVS_CLK] = imx_clk_hw_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);

	hws[IMX7D_MU_ROOT_CLK] = imx_clk_hw_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0);

	hws[IMX7D_CAAM_CLK] = imx_clk_hw_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);

	hws[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_hw_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);