Commit 2c29798c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ti', 'clk-cleanup', 'clk-airoha', 'clk-i2c-simple' and... 

Merge branches 'clk-ti', 'clk-cleanup', 'clk-airoha', 'clk-i2c-simple' and 'clk-renesas' into clk-next

 - Airoha EN7523 SoC system clocks
 - Use i2c driver probe_new to avoid id scans

* clk-ti:
  clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
  clk: ti: composite: Prefer kcalloc over open coded arithmetic
  clk: keystone: syscon-clk: Add support for AM62 epwm-tbclk
  dt-bindings: clock: ehrpwm: Add AM62 specific compatible

* clk-cleanup:
  clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
  clk: fixed-rate: Remove redundant if statement
  clk: mux: remove redundant initialization of variable width
  clk: using pm_runtime_resume_and_get instead of pm_runtime_get_sync
  clk: actions: remove redundant assignment after a mask operation

* clk-airoha:
  clk: en7523: fix wrong pointer check in en7523_clk_probe()
  clk: en7523: Add clock driver for Airoha EN7523 SoC
  dt-bindings: Add en7523-scu device tree binding documentation

* clk-i2c-simple:
  clk: renesas-pcie: use simple i2c probe function
  clk: si570: use i2c_match_id and simple i2c probe
  clk: si544: use i2c_match_id and simple i2c probe
  clk: si5351: use i2c_match_id and simple i2c probe
  clk: si5341: use simple i2c probe function
  clk: si514: use simple i2c probe function
  clk: max9485: use simple i2c probe function
  clk: cs2000-cp: use simple i2c probe function
  clk: cdce925: use i2c_match_id and simple i2c probe
  clk: cdce706: use simple i2c probe function

* clk-renesas: (48 commits)
  clk: renesas: r9a09g011: Add eth clock and reset entries
  clk: renesas: Add RZ/V2M support using the rzg2l driver
  clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
  clk: renesas: rzg2l: Make use of CLK_MON registers optional
  clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
  clk: renesas: rzg2l: Add read only versions of the clk macros
  clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
  dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
  clk: renesas: r9a07g044: Fix OSTM1 module clock name
  clk: renesas: r9a07g043: Add clock and reset entries for ADC
  clk: renesas: r9a07g043: Add TSU clock and reset entry
  clk: renesas: r9a07g043: Add RSPI clock and reset entries
  clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller
  clk: renesas: r9a07g044: Add DSI clock and reset entries
  clk: renesas: r9a07g044: Add LCDC clock and reset entries
  clk: renesas: r9a07g044: Add M4 Clock support
  clk: renesas: r9a07g044: Add M3 Clock support
  clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
  clk: renesas: r9a07g044: Add M1 clock support
  clk: renesas: rzg2l: Add DSI divider clk support
  ...
parents 560a3164 b7fa6242 c6b61d48 5baa12cf 13982e86

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: EN7523 Clock Device Tree Bindings



maintainers:

  - Felix Fietkau <nbd@nbd.name>

  - John Crispin <nbd@nbd.name>



description: |

  This node defines the System Control Unit of the EN7523 SoC,

  a collection of registers configuring many different aspects of the SoC.



  The clock driver uses it to read and configure settings of the

  PLL controller, which provides clocks for the CPU, the bus and

  other SoC internal peripherals.



  Each clock is assigned an identifier and client nodes use this identifier

  to specify which clock they consume.



  All these identifiers can be found in:

  [1]: <include/dt-bindings/clock/en7523-clk.h>.



  The clocks are provided inside a system controller node.



properties:

  compatible:

    items:

      - const: airoha,en7523-scu



  reg:

    maxItems: 2



  "#clock-cells":

    description:

      The first cell indicates the clock number, see [1] for available

      clocks.

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/en7523-clk.h>

    scu: system-controller@1fa20000 {

      compatible = "airoha,en7523-scu";

      reg = <0x1fa20000 0x400>,

            <0x1fb00000 0x1000>;

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+1 −0
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@@ -49,6 +49,7 @@ properties: 
      - renesas,r8a77995-cpg-mssr # R-Car D3

      - renesas,r8a779a0-cpg-mssr # R-Car V3U

      - renesas,r8a779f0-cpg-mssr # R-Car S4-8

      - renesas,r8a779g0-cpg-mssr # R-Car V4H



  reg:

    maxItems: 1

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+12 −8
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@@ -4,14 +4,15 @@ 
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode

title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.

  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block. On RZ/V2M, the functionality is

  similar, but does not have Clock Monitor Registers.



  They provide the following functionalities:

    - The CPG block generates various core clocks,
@@ -23,8 +24,10 @@ description: | 
properties:

  compatible:

    enum:

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a09g011-cpg # RZ/V2M



  reg:

    maxItems: 1
@@ -42,9 +45,10 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g*-cpg.h>

        <dt-bindings/clock/r9a0*-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or

        <dt-bindings/clock/r9a09g011-cpg.h>.

    const: 2



  '#power-domain-cells':
@@ -58,7 +62,7 @@ properties: 
  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g0*-cpg.h>.

      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.

    const: 1



required:

drivers/clk/Kconfig

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@@ -210,6 +210,15 @@ config COMMON_CLK_CS2000_CP 
	help

	  If you say yes here you get support for the CS2000 clock multiplier.



config COMMON_CLK_EN7523

	bool "Clock driver for Airoha EN7523 SoC system clocks"

	depends on OF

	depends on ARCH_AIROHA || COMPILE_TEST

	default ARCH_AIROHA

	help

	  This driver provides the fixed clocks and gates present on Airoha

	  ARM silicon.



config COMMON_CLK_FSL_FLEXSPI

	tristate "Clock driver for FlexSPI on Layerscape SoCs"

	depends on ARCH_LAYERSCAPE || COMPILE_TEST

drivers/clk/Makefile

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@@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o 
obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o

obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o

obj-$(CONFIG_ARCH_SPARX5)		+= clk-sparx5.o

obj-$(CONFIG_COMMON_CLK_EN7523)		+= clk-en7523.o

obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)	+= clk-fixed-mmio.o

obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI)	+= clk-fsl-flexspi.o

obj-$(CONFIG_COMMON_CLK_FSL_SAI)	+= clk-fsl-sai.o