Commit 13982e86 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.19-tag2' of... 

Merge tag 'renesas-clk-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the R-Car V4H and RZ/V2M SoCs
 - Add the Universal Flash Storage clock on R-Car S4-8
 - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
   I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on RZ/G2UL
 - Add display clock support on RZ/G2L
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (36 commits)
  clk: renesas: r9a09g011: Add eth clock and reset entries
  clk: renesas: Add RZ/V2M support using the rzg2l driver
  clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
  clk: renesas: rzg2l: Make use of CLK_MON registers optional
  clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
  clk: renesas: rzg2l: Add read only versions of the clk macros
  clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
  dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
  clk: renesas: r9a07g044: Fix OSTM1 module clock name
  clk: renesas: r9a07g043: Add clock and reset entries for ADC
  clk: renesas: r9a07g043: Add TSU clock and reset entry
  clk: renesas: r9a07g043: Add RSPI clock and reset entries
  clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller
  clk: renesas: r9a07g044: Add DSI clock and reset entries
  clk: renesas: r9a07g044: Add LCDC clock and reset entries
  clk: renesas: r9a07g044: Add M4 Clock support
  clk: renesas: r9a07g044: Add M3 Clock support
  clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
  clk: renesas: r9a07g044: Add M1 clock support
  clk: renesas: rzg2l: Add DSI divider clk support
  ...
parents 9f4f53ef 23426d1b

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ properties: 
      - renesas,r8a77995-cpg-mssr # R-Car D3

      - renesas,r8a779a0-cpg-mssr # R-Car V3U

      - renesas,r8a779f0-cpg-mssr # R-Car S4-8

      - renesas,r8a779g0-cpg-mssr # R-Car V4H



  reg:

    maxItems: 1

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+8 −5
Original line number Diff line number Diff line
@@ -4,14 +4,15 @@ 
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode

title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.

  Standby Mode share the same register block. On RZ/V2M, the functionality is

  similar, but does not have Clock Monitor Registers.



  They provide the following functionalities:

    - The CPG block generates various core clocks,
@@ -26,6 +27,7 @@ properties: 
      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a09g011-cpg # RZ/V2M



  reg:

    maxItems: 1
@@ -43,9 +45,10 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g*-cpg.h>

        <dt-bindings/clock/r9a0*-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or

        <dt-bindings/clock/r9a09g011-cpg.h>.

    const: 2



  '#power-domain-cells':
@@ -59,7 +62,7 @@ properties: 
  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g0*-cpg.h>.

      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.

    const: 1



required:

drivers/clk/renesas/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -32,10 +32,12 @@ config CLK_RENESAS 
	select CLK_R8A77995 if ARCH_R8A77995

	select CLK_R8A779A0 if ARCH_R8A779A0

	select CLK_R8A779F0 if ARCH_R8A779F0

	select CLK_R8A779G0 if ARCH_R8A779G0

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_R9A07G043 if ARCH_R9A07G043

	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_R9A09G011 if ARCH_R9A09G011

	select CLK_SH73A0 if ARCH_SH73A0



if CLK_RENESAS
@@ -158,6 +160,10 @@ config CLK_R8A779F0 
	bool "R-Car S4-8 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN4_CPG



config CLK_R8A779G0

	bool "R-Car V4H clock support" if COMPILE_TEST

	select CLK_RCAR_GEN4_CPG



config CLK_R9A06G032

	bool "RZ/N1D clock support" if COMPILE_TEST
@@ -173,6 +179,10 @@ config CLK_R9A07G054 
	bool "RZ/V2L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A09G011

	bool "RZ/V2M clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_SH73A0

	bool "SH-Mobile AG5 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP

drivers/clk/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -29,10 +29,12 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779A0)		+= r8a779a0-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779G0)		+= r8a779g0-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_R9A07G043)		+= r9a07g043-cpg.o

obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+6 −6
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 
/*

 *   MD	 EXTAL		PLL1	PLL20	PLL30	PLL4	PLL5	OSC

 * 14 13 (MHz)			   21	   31

 * --------------------------------------------------------

 * ----------------------------------------------------------------

 * 0  0	 16.66 x 1	x128	x216	x128	x144	x192	/16

 * 0  1	 20    x 1	x106	x180	x106	x120	x160	/19

 * 1  0	 Prohibited setting
@@ -253,11 +253,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 
#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \

					 (((md) & BIT(13)) >> 13))

static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {

	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */

	{ 1,		128,	1,	0,	0,	0,	0,	192,	1,	0,	0,	16,	},

	{ 1,		106,	1,	0,	0,	0,	0,	160,	1,	0,	0,	19,	},

	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},

	{ 2,		128,	1,	0,	0,	0,	0,	192,	1,	0,	0,	32,	},

	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */

	{ 1,		128,	1,	0,	0,	0,	0,	144,	1,	192,	1,	0,	0,	16,	},

	{ 1,		106,	1,	0,	0,	0,	0,	120,	1,	160,	1,	0,	0,	19,	},

	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},

	{ 2,		128,	1,	0,	0,	0,	0,	144,	1,	192,	1,	0,	0,	32,	},

};