Commit 9f4f53ef authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.19-tag1' of... 

Merge tag 'renesas-clk-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the new RZ/G2UL SoC
 - Add RPC (QSPI/HyperFlash) clocks on R-Car E3 and D3
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a07g043: Add SDHI clock and reset entries
  clk: renesas: r9a07g043: Add GbEthernet clock/reset
  clk: renesas: r9a07g043: Add ethernet clock sources
  clk: renesas: r9a07g043: Add GPIO clock and reset entries
  clk: renesas: Add support for RZ/G2UL SoC
  clk: renesas: Move RPC core clocks
  clk: renesas: rzg2l: Simplify multiplication/shift logic
  dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
  clk: renesas: r8a77995: Add RPC clocks
  clk: renesas: r8a77990: Add RPC clocks
  dt-bindings: clock: renesas: Document RZ/G2UL SoC
  clk: renesas: rzg2l: Remove unused notifiers
parents 31231092 59086e41

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+4 −3
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ maintainers: 
  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module

  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.



  They provide the following functionalities:
@@ -23,6 +23,7 @@ description: | 
properties:

  compatible:

    enum:

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ config CLK_RENESAS 
	select CLK_R8A779A0 if ARCH_R8A779A0

	select CLK_R8A779F0 if ARCH_R8A779F0

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_R9A07G043 if ARCH_R9A07G043

	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_SH73A0 if ARCH_SH73A0
@@ -160,6 +161,10 @@ config CLK_R8A779F0 
config CLK_R9A06G032

	bool "RZ/N1D clock support" if COMPILE_TEST



config CLK_R9A07G043

	bool "RZ/G2UL clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A07G044

	bool "RZ/G2L clock support" if COMPILE_TEST

	select CLK_RZG2L
@@ -200,7 +205,7 @@ config CLK_RCAR_USB2_CLOCK_SEL 
	  This is a driver for R-Car USB2 clock selector



config CLK_RZG2L

	bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST

	bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



# Generic

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A779A0)		+= r8a779a0-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_R9A07G043)		+= r9a07g043-cpg.o

obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+4 −5
Original line number Diff line number Diff line
@@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),

	DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_BASE("rpc",         R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,

		 CLK_RPCSRC),

	DEF_BASE("rpcd2",       R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,

		 R8A774A1_CLK_RPC),

	DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
@@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	DEF_GEN3_SD("sd2",      R8A774A1_CLK_SD2,   R8A774A1_CLK_SD2H, 0x268),

	DEF_GEN3_SD("sd3",      R8A774A1_CLK_SD3,   R8A774A1_CLK_SD3H, 0x26c),



	DEF_BASE("rpc",         R8A774A1_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),

	DEF_BASE("rpcd2",       R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC),



	DEF_FIXED("cl",         R8A774A1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A774A1_CLK_CPEX,  CLK_EXTAL,      2, 1),

drivers/clk/renesas/r8a774b1-cpg-mssr.c

+4 −5
Original line number Diff line number Diff line
@@ -66,12 +66,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { 
	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),

	DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_BASE("rpc",         R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,

		 CLK_RPCSRC),

	DEF_BASE("rpcd2",       R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,

		 R8A774B1_CLK_RPC),

	DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
@@ -106,6 +102,9 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { 
	DEF_GEN3_SD("sd2",      R8A774B1_CLK_SD2,   R8A774B1_CLK_SD2H, 0x268),

	DEF_GEN3_SD("sd3",      R8A774B1_CLK_SD3,   R8A774B1_CLK_SD3H, 0x26c),



	DEF_BASE("rpc",         R8A774B1_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),

	DEF_BASE("rpcd2",       R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),



	DEF_FIXED("cl",         R8A774B1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A774B1_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A774B1_CLK_CPEX,  CLK_EXTAL,      2, 1),