ARM: 9057/1: cache-v7: add missing ISB after cache level selection

mainline inclusion
from mainline-v5.15-rc2
commit c0e50736
bugzilla: 185697 https://gitee.com/openeuler/kernel/issues/I4DDEL

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c0e50736e826b51ddc437e6cf0dc68f07e4ad16b



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A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: He Ying <heying24@huawei.com>
Reviewed-by: Liao Chang <liaochang1@huawei.com>
Reviewed-by: Li Wei <liwei391@huawei.com>

Signed-off-by: Chen Jun <chenjun102@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>