Commit c0e50736 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Russell King
Browse files

ARM: 9057/1: cache-v7: add missing ISB after cache level selection 



A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: default avatarNicolas Pitre <nico@fluxnic.net>
Signed-off-by: default avatarArd Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent c4e792d1

arch/arm/mm/cache-v7.S

+4 −3
Original line number Diff line number Diff line
@@ -39,8 +39,9 @@ icache_size: 
 */

ENTRY(v7_invalidate_l1)

	mov	r0, #0

       mcr     p15, 2, r0, c0, c0, 0

       mrc     p15, 1, r0, c0, c0, 0

	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR

	isb

	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR



       movw    r1, #0x7fff

       and     r2, r1, r0, lsr #13