perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support

mainline inclusion
from mainline-v5.15-rc1
commit f85ef898
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO



Intel-SIG: commit f85ef898 perf/x86/intel/uncore: Add Sapphire
Rapids server M2PCIe support
This commit is backported for SPR PMU uncore support.

-------------------------------------

M2PCIe* blocks manage the interface between the mesh and each IIO stack.

The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>