Commit f85ef898 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support 



M2PCIe* blocks manage the interface between the mesh and each IIO stack.

The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com
parent e199eb51

arch/x86/events/intel/uncore_snbep.c

+6 −1
Original line number Diff line number Diff line
@@ -5628,13 +5628,18 @@ static struct intel_uncore_type spr_uncore_irp = { 


};



static struct intel_uncore_type spr_uncore_m2pcie = {

	SPR_UNCORE_COMMON_FORMAT(),

	.name			= "m2pcie",

};



#define UNCORE_SPR_NUM_UNCORE_TYPES		12



static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {

	&spr_uncore_chabox,

	&spr_uncore_iio,

	&spr_uncore_irp,

	NULL,

	&spr_uncore_m2pcie,

	NULL,

	NULL,

	NULL,