perf/x86/intel/uncore: Fix Intel SPR CHA event constraints

mainline inclusion
from mainline-v5.16-rc1
commit 9d756e40
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO



Intel-SIG: commit 9d756e40 perf/x86/intel/uncore: Fix Intel SPR CHA
event constraints
This commit is backported as a fix to SPR PMU uncore support.

-------------------------------------

SPR CHA events have the exact same event constraints as SKX, so add the
constraints.

Fixes: 949b1138 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-5-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>