Commit c19c6c7b authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next 

* clk-of:
  clk: add missing of_node_put() in "assigned-clocks" property parsing

* clk-samsung:
  clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
  clk: samsung: Convert to platform remove callback returning void
  clk: samsung: exynos5433: Extract PM support to common ARM64 layer
  clk: samsung: Extract parent clock enabling to common function
  clk: samsung: Extract clocks registration to common function
  clk: samsung: exynos850: Add AUD and HSI main gate clocks
  clk: samsung: exynos850: Implement CMU_G3D domain
  clk: samsung: clk-pll: Implement pll0818x PLL type
  clk: samsung: Set dev in samsung_clk_init()
  clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
  clk: samsung: Remove np argument from samsung_clk_init()
  dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
  dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D

* clk-rockchip:
  clk: rockchip: rk3588: make gate linked clocks critical
  clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent

* clk-qcom: (57 commits)
  clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
  clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
  clk: qcom: add the GPUCC driver for sa8775p
  dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
  clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
  clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
  clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
  dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
  clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  dt-bindings: clock: Add ipq9574 clock and reset definitions
  clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
  clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
  clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
  dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
  clk: qcom: apss-ipq-pll: add support for IPQ5332
  dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
  clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
  dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
  dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
  ...
parents 1a86e99f 27a6e1b0 ef382228 0818c8d4 ea90f303

Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt

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Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)



The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.

There is one ACC register region per CPU within the KPSS remapped region as

well as an alias register region that remaps accesses to the ACC associated

with the CPU accessing the region.



PROPERTIES



- compatible:

	Usage: required

	Value type: <string>

	Definition: should be one of:

			"qcom,kpss-acc-v1"

			"qcom,kpss-acc-v2"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: the first element specifies the base address and size of

		    the register region. An optional second element specifies

		    the base address and size of the alias register region.



- clocks:

        Usage: required

        Value type: <prop-encoded-array>

        Definition: reference to the pll parents.



- clock-names:

        Usage: required

        Value type: <stringlist>

        Definition: must be "pll8_vote", "pxo".



- clock-output-names:

	Usage: optional

	Value type: <string>

	Definition: Name of the output clock. Typically acpuX_aux where X is a

		    CPU number starting at 0.



Example:



	clock-controller@2088000 {

		compatible = "qcom,kpss-acc-v2";

		reg = <0x02088000 0x1000>,

		      <0x02008000 0x1000>;

		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;

		clock-names = "pll8_vote", "pxo";

		clock-output-names = "acpu0_aux";

	};

Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

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Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)



PROPERTIES



- compatible:

	Usage: required

	Value type: <string>

	Definition: should be one of the following. The generic compatible

			"qcom,kpss-gcc" should also be included.

			"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"

			"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"

			"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"

			"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: base address and size of the register region



- clocks:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: reference to the pll parents.



- clock-names:

	Usage: required

	Value type: <stringlist>

	Definition: must be "pll8_vote", "pxo".



- clock-output-names:

	Usage: required

	Value type: <string>

	Definition: Name of the output clock. Typically acpu_l2_aux indicating

		    an L2 cache auxiliary clock.



Example:



	l2cc: clock-controller@2011000 {

		compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";

		reg = <0x2011000 0x1000>;

		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;

		clock-names = "pll8_vote", "pxo";

		clock-output-names = "acpu_l2_aux";

	};

Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

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@@ -16,6 +16,7 @@ description: 
properties:

  compatible:

    enum:

      - qcom,ipq5332-a53pll

      - qcom,ipq6018-a53pll

      - qcom,ipq8074-a53pll

      - qcom,msm8916-a53pll

Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on IPQ4019



maintainers:

  - Stephen Boyd <sboyd@kernel.org>

  - Taniya Das <tdas@codeaurora.org>

  - Robert Marko <robert.markoo@sartura.hr>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on IPQ4019.



  See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h



allOf:

  - $ref: qcom,gcc.yaml#



properties:

  compatible:

    const: qcom,gcc-ipq4019



  clocks:

    items:

      - description: board XO clock

      - description: sleep clock



  clock-names:

    items:

      - const: xo

      - const: sleep_clk



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    clock-controller@1800000 {

      compatible = "qcom,gcc-ipq4019";

      reg = <0x1800000 0x60000>;

      #clock-cells = <1>;

      #power-domain-cells = <1>;

      #reset-cells = <1>;

      clocks = <&xo>, <&sleep_clk>;

      clock-names = "xo", "sleep_clk";

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml

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@@ -4,20 +4,25 @@ 
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on MSM8909

title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215



maintainers:

  - Stephan Gerhold <stephan@gerhold.net>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on MSM8909.

  domains on MSM8909, MSM8917 or QM215.



  See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h

  See also::

    include/dt-bindings/clock/qcom,gcc-msm8909.h

    include/dt-bindings/clock/qcom,gcc-msm8917.h



properties:

  compatible:

    const: qcom,gcc-msm8909

    enum:

      - qcom,gcc-msm8909

      - qcom,gcc-msm8917

      - qcom,gcc-qm215



  clocks:

    items: