Commit 1a86e99f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-starfive', 'clk-fractional' and 'clk-devmof' into clk-next 

 - Shrink size of clk_fractional_divider a little
 - Convert various clk drivers to devm_of_clk_add_hw_provider()

* clk-starfive:
  clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
  clk: starfive: Avoid casting iomem pointers
  MAINTAINERS: generalise StarFive clk/reset entries
  reset: starfive: Add StarFive JH7110 reset driver
  clk: starfive: Add StarFive JH7110 always-on clock driver
  clk: starfive: Add StarFive JH7110 system clock driver
  reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
  reset: starfive: Rename "jh7100" to "jh71x0" for the common code
  reset: starfive: Extract the common JH71X0 reset code
  reset: starfive: Factor out common JH71X0 reset code
  reset: Create subdirectory for StarFive drivers
  reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
  clk: starfive: Rename "jh7100" to "jh71x0" for the common code
  clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
  clk: starfive: Factor out common JH7100 and JH7110 code
  clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
  dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

* clk-fractional:
  clk: Remove mmask and nmask fields in struct clk_fractional_divider
  clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider
  clk: imx: Remove values for mmask and nmask in struct clk_fractional_divider
  clk: Compute masks for fractional_divider clk when needed.

* clk-devmof:
  clk: uniphier: Use managed `of_clk_add_hw_provider()`
  clk: si5351: Use managed `of_clk_add_hw_provider()`
  clk: si570: Use managed `of_clk_add_hw_provider()`
  clk: si514: Use managed `of_clk_add_hw_provider()`
  clk: lmk04832: Use managed `of_clk_add_hw_provider()`
  clk: hsdk-pll: Use managed `of_clk_add_hw_provider()`
  clk: cdce706: Use managed `of_clk_add_hw_provider()`
  clk: axs10x: Use managed `of_clk_add_hw_provider()`
  clk: axm5516: Use managed `of_clk_add_hw_provider()`
  clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`
parents caca6ad3 c19d966e 14e98548 c0e19528

Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Always-On Clock and Reset Generator



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7110-aoncrg



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference or GMAC0 RGMII RX

          - description: STG AXI/AHB

          - description: APB Bus

          - description: GMAC0 GTX



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference or GMAC0 RGMII RX

          - description: STG AXI/AHB or GMAC0 RGMII RX

          - description: APB Bus or STG AXI/AHB

          - description: GMAC0 GTX or APB Bus

          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference

          - description: GMAC0 RGMII RX

          - description: STG AXI/AHB

          - description: APB Bus

          - description: GMAC0 GTX

          - description: RTC Oscillator (32.768 kHz)



  clock-names:

    oneOf:

      - minItems: 5

        items:

          - const: osc

          - enum:

              - gmac0_rmii_refin

              - gmac0_rgmii_rxin

          - const: stg_axiahb

          - const: apb_bus

          - const: gmac0_gtxclk

          - const: rtc_osc



      - minItems: 6

        items:

          - const: osc

          - const: gmac0_rmii_refin

          - const: gmac0_rgmii_rxin

          - const: stg_axiahb

          - const: apb_bus

          - const: gmac0_gtxclk

          - const: rtc_osc



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>



    clock-controller@17000000 {

        compatible = "starfive,jh7110-aoncrg";

        reg = <0x17000000 0x10000>;

        clocks = <&osc>, <&gmac0_rmii_refin>,

                 <&gmac0_rgmii_rxin>,

                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,

                 <&syscrg JH7110_SYSCLK_APB_BUS>,

                 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,

                 <&rtc_osc>;

        clock-names = "osc", "gmac0_rmii_refin",

                      "gmac0_rgmii_rxin", "stg_axiahb",

                      "apb_bus", "gmac0_gtxclk",

                      "rtc_osc";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 System Clock and Reset Generator



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7110-syscrg



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC1 RMII reference or GMAC1 RGMII RX

          - description: External I2S TX bit clock

          - description: External I2S TX left/right channel clock

          - description: External I2S RX bit clock

          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC1 RMII reference

          - description: GMAC1 RGMII RX

          - description: External I2S TX bit clock

          - description: External I2S TX left/right channel clock

          - description: External I2S RX bit clock

          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock



  clock-names:

    oneOf:

      - items:

          - const: osc

          - enum:

              - gmac1_rmii_refin

              - gmac1_rgmii_rxin

          - const: i2stx_bclk_ext

          - const: i2stx_lrck_ext

          - const: i2srx_bclk_ext

          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext



      - items:

          - const: osc

          - const: gmac1_rmii_refin

          - const: gmac1_rgmii_rxin

          - const: i2stx_bclk_ext

          - const: i2stx_lrck_ext

          - const: i2srx_bclk_ext

          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    clock-controller@13020000 {

        compatible = "starfive,jh7110-syscrg";

        reg = <0x13020000 0x10000>;

        clocks = <&osc>, <&gmac1_rmii_refin>,

                 <&gmac1_rgmii_rxin>,

                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

                 <&tdm_ext>, <&mclk_ext>;

        clock-names = "osc", "gmac1_rmii_refin",

                      "gmac1_rgmii_rxin",

                      "i2stx_bclk_ext", "i2stx_lrck_ext",

                      "i2srx_bclk_ext", "i2srx_lrck_ext",

                      "tdm_ext", "mclk_ext";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

MAINTAINERS

+12 −10
Original line number Diff line number Diff line
@@ -19908,19 +19908,20 @@ M: Emil Renner Berthing <kernel@esmil.dk> 
S:	Maintained

F:	arch/riscv/boot/dts/starfive/









STARFIVE JH7100 CLOCK DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml









F:	drivers/clk/starfive/clk-starfive-jh7100*









F:	include/dt-bindings/clock/starfive-jh7100*.h

















STARFIVE JH7110 MMC/SD/SDIO DRIVER









M:	William Qiu <william.qiu@starfivetech.com>









S:	Supported









F:	Documentation/devicetree/bindings/mmc/starfive*









F:	drivers/mmc/host/dw_mmc-starfive.c

















STARFIVE JH71X0 CLOCK DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Hal Feng <hal.feng@starfivetech.com>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/starfive,jh71*.yaml









F:	drivers/clk/starfive/clk-starfive-jh71*









F:	include/dt-bindings/clock/starfive?jh71*.h

















STARFIVE JH71X0 PINCTRL DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Jianlong Huang <jianlong.huang@starfivetech.com>








@@ -19931,12 +19932,13 @@ F:	drivers/pinctrl/starfive/pinctrl-starfive-jh71*







F:	include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h









F:	include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h

















STARFIVE JH7100 RESET CONTROLLER DRIVER









STARFIVE JH71X0 RESET CONTROLLER DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Hal Feng <hal.feng@starfivetech.com>









S:	Maintained









F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml









F:	drivers/reset/reset-starfive-jh7100.c









F:	include/dt-bindings/reset/starfive-jh7100.h









F:	drivers/reset/starfive/reset-starfive-jh71*









F:	include/dt-bindings/reset/starfive?jh71*.h

















STARFIVE JH71XX PMU CONTROLLER DRIVER









M:	Walker Chen <walker.chen@starfivetech.com>

























drivers/clk/Makefile



+1
−1






























Original line number
Diff line number
Diff line







@@ -120,7 +120,7 @@ obj-$(CONFIG_PLAT_SPEAR)		+= spear/







obj-y					+= sprd/









obj-$(CONFIG_ARCH_STI)			+= st/









obj-$(CONFIG_ARCH_STM32)		+= stm32/









obj-$(CONFIG_SOC_STARFIVE)		+= starfive/









obj-y					+= starfive/









obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/









obj-y					+= sunxi-ng/









obj-$(CONFIG_ARCH_TEGRA)		+= tegra/
































drivers/clk/axs10x/pll_clock.c



+2
−8






























Original line number
Diff line number
Diff line







@@ -253,15 +253,10 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev)







		return ret;









	}



















	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,









	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,









					   &pll_clk->hw);









}



















static void axs10x_pll_clk_remove(struct platform_device *pdev)









{









	of_clk_del_provider(pdev->dev.of_node);









}



















static void __init of_axs10x_pll_clk_setup(struct device_node *node)









{









	const char *parent_name;








@@ -331,7 +326,6 @@ static struct platform_driver axs10x_pll_clk_driver = {







		.of_match_table = axs10x_pll_clk_id,









	},









	.probe = axs10x_pll_clk_probe,









	.remove_new = axs10x_pll_clk_remove,









};









builtin_platform_driver(axs10x_pll_clk_driver);