Commit 0818c8d4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v6.4-rockchip-clk1' of... 

Merge tag 'v6.4-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull a couple Rockchip clk driver updates from Heiko Stübner:

Reparenting fix for the clock supplying camera modules on the rk3399
and more critical (bus-)clocks on the rk3588.

* tag 'v6.4-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3588: make gate linked clocks critical
  clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
parents fe15c26e 64042c28

drivers/clk/rockchip/clk-rk3399.c

+1 −1
Original line number Diff line number Diff line
@@ -1263,7 +1263,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,

			RK3399_CLKGATE_CON(10), 7, GFLAGS),



	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,

	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,

			 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),



	/* gic */

drivers/clk/rockchip/clk-rk3588.c

+26 −16
Original line number Diff line number Diff line
@@ -13,15 +13,25 @@ 
#include "clk.h"



/*

 * GATE with additional linked clock. Downstream enables the linked clock

 * (via runtime PM) whenever the gate is enabled. The downstream implementation

 * does this via separate clock nodes for each of the linked gate clocks,

 * which leaks parts of the clock tree into DT. It is unclear why this is

 * actually needed and things work without it for simple use cases. Thus

 * the linked clock is ignored for now.

 * Recent Rockchip SoCs have a new hardware block called Native Interface

 * Unit (NIU), which gates clocks to devices behind them. These effectively

 * need two parent clocks.

 *

 * Downstream enables the linked clock via runtime PM whenever the gate is

 * enabled. This implementation uses separate clock nodes for each of the

 * linked gate clocks, which leaks parts of the clock tree into DT.

 *

 * The GATE_LINK macro instead takes the second parent via 'linkname', but

 * ignores the information. Once the clock framework is ready to handle it, the

 * information should be passed on here. But since these clocks are required to

 * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked

 * clocks critical until a better solution is available. This will waste some

 * power, but avoids leaking implementation details into DT or hanging the

 * system.

 */

#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \

	GATE(_id, cname, pname, f, o, b, gf)

#define RK3588_LINKED_CLK		CLK_IS_CRITICAL





#define RK3588_GRF_SOC_STATUS0		0x600
@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
	COMPOSITE_NODIV(HCLK_NVM_ROOT,  "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,

			RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,

			RK3588_CLKGATE_CON(31), 0, GFLAGS),

	COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,

	COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,

			RK3588_CLKGATE_CON(31), 1, GFLAGS),

	GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
			RK3588_CLKGATE_CON(42), 9, GFLAGS),



	/* vdpu */

	COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,

	COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,

			RK3588_CLKGATE_CON(44), 0, GFLAGS),

	COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,

			RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,

			RK3588_CLKGATE_CON(44), 1, GFLAGS),

	COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,

	COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,

			RK3588_CLKGATE_CON(44), 2, GFLAGS),

	COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
	COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,

			RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,

			RK3588_CLKGATE_CON(47), 1, GFLAGS),

	GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,

	GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,

			RK3588_CLKGATE_CON(47), 4, GFLAGS),

	GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,

	GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,

			RK3588_CLKGATE_CON(47), 5, GFLAGS),

	COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,

			RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
			RK3588_CLKGATE_CON(48), 6, GFLAGS),



	/* vi */

	COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,

	COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,

			RK3588_CLKGATE_CON(49), 0, GFLAGS),

	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,

	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,

			RK3588_CLKGATE_CON(49), 1, GFLAGS),

	COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
	COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,

			RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,

			RK3588_CLKGATE_CON(52), 0, GFLAGS),

	COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,

	COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,

			RK3588_CLKGATE_CON(52), 1, GFLAGS),

	COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,

	COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,

			RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,

			RK3588_CLKGATE_CON(52), 2, GFLAGS),

	COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 


	GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),

	GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),

	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),

	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),

	GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),

	GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),

	GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),