Commit c17f8fd3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-5.19-2' of... 

Merge tag 'qcom-clk-for-5.19-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull some Qualcomm clock driver reverts from Bjorn Andersson:

After concerns were raised about the new PCIe pipe_clk mux
implementation an updated implementation has evolved, but has not yet
been accepted.

This reverts the merged changes to avoid these concerns in the current
release.

* tag 'qcom-clk-for-5.19-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  Revert "clk: qcom: regmap-mux: add pipe clk implementation"
  Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
parents 856c7986 03e053b4

drivers/clk/qcom/clk-regmap-mux.c

+0 −78
Original line number Diff line number Diff line
@@ -49,87 +49,9 @@ static int mux_set_parent(struct clk_hw *hw, u8 index) 
	return regmap_update_bits(clkr->regmap, mux->reg, mask, val);

}



static u8 mux_safe_get_parent(struct clk_hw *hw)

{

	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);

	unsigned int val;



	if (clk_hw_is_enabled(hw))

		return mux_get_parent(hw);



	val = mux->stored_parent_cfg;



	if (mux->parent_map)

		return qcom_find_cfg_index(hw, mux->parent_map, val);



	return val;

}



static int mux_safe_set_parent(struct clk_hw *hw, u8 index)

{

	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);



	if (clk_hw_is_enabled(hw))

		return mux_set_parent(hw, index);



	if (mux->parent_map)

		index = mux->parent_map[index].cfg;



	mux->stored_parent_cfg = index;



	return 0;

}



static void mux_safe_disable(struct clk_hw *hw)

{

	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);

	struct clk_regmap *clkr = to_clk_regmap(hw);

	unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);

	unsigned int val;



	regmap_read(clkr->regmap, mux->reg, &val);



	mux->stored_parent_cfg = (val & mask) >> mux->shift;



	val = mux->safe_src_parent;

	if (mux->parent_map) {

		int index = qcom_find_src_index(hw, mux->parent_map, val);



		if (WARN_ON(index < 0))

			return;



		val = mux->parent_map[index].cfg;

	}

	val <<= mux->shift;



	regmap_update_bits(clkr->regmap, mux->reg, mask, val);

}



static int mux_safe_enable(struct clk_hw *hw)

{

	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);

	struct clk_regmap *clkr = to_clk_regmap(hw);

	unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);

	unsigned int val;



	val = mux->stored_parent_cfg;

	val <<= mux->shift;



	return regmap_update_bits(clkr->regmap, mux->reg, mask, val);

}



const struct clk_ops clk_regmap_mux_closest_ops = {

	.get_parent = mux_get_parent,

	.set_parent = mux_set_parent,

	.determine_rate = __clk_mux_determine_rate_closest,

};

EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
 


const struct clk_ops clk_regmap_mux_safe_ops = {

	.enable = mux_safe_enable,

	.disable = mux_safe_disable,

	.get_parent = mux_safe_get_parent,

	.set_parent = mux_safe_set_parent,

	.determine_rate = __clk_mux_determine_rate_closest,

};

EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops);

drivers/clk/qcom/clk-regmap-mux.h

+0 −3
Original line number Diff line number Diff line
@@ -14,13 +14,10 @@ struct clk_regmap_mux { 
	u32			reg;

	u32			shift;

	u32			width;

	u8			safe_src_parent;

	u8			stored_parent_cfg;

	const struct parent_map	*parent_map;

	struct clk_regmap	clkr;

};



extern const struct clk_ops clk_regmap_mux_closest_ops;

extern const struct clk_ops clk_regmap_mux_safe_ops;



#endif

drivers/clk/qcom/gcc-sc7280.c

+2 −4
Original line number Diff line number Diff line
@@ -373,14 +373,13 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 
	.reg = 0x6b054,

	.shift = 0,

	.width = 2,

	.safe_src_parent = P_BI_TCXO,

	.parent_map = gcc_parent_map_6,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_pipe_clk_src",

			.parent_data = gcc_parent_data_6,

			.num_parents = ARRAY_SIZE(gcc_parent_data_6),

			.ops = &clk_regmap_mux_safe_ops,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};
@@ -389,14 +388,13 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { 
	.reg = 0x8d054,

	.shift = 0,

	.width = 2,

	.safe_src_parent = P_BI_TCXO,

	.parent_map = gcc_parent_map_7,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_pipe_clk_src",

			.parent_data = gcc_parent_data_7,

			.num_parents = ARRAY_SIZE(gcc_parent_data_7),

			.ops = &clk_regmap_mux_safe_ops,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};

drivers/clk/qcom/gcc-sm8450.c

+2 −4
Original line number Diff line number Diff line
@@ -243,14 +243,13 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 
	.reg = 0x7b060,

	.shift = 0,

	.width = 2,

	.safe_src_parent = P_BI_TCXO,

	.parent_map = gcc_parent_map_4,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_pipe_clk_src",

			.parent_data = gcc_parent_data_4,

			.num_parents = ARRAY_SIZE(gcc_parent_data_4),

			.ops = &clk_regmap_mux_safe_ops,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};
@@ -274,14 +273,13 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { 
	.reg = 0x9d064,

	.shift = 0,

	.width = 2,

	.safe_src_parent = P_BI_TCXO,

	.parent_map = gcc_parent_map_6,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_pipe_clk_src",

			.parent_data = gcc_parent_data_6,

			.num_parents = ARRAY_SIZE(gcc_parent_data_6),

			.ops = &clk_regmap_mux_safe_ops,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};