Commit aca38735 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2021-04-22' of... 

Merge tag 'drm-intel-fixes-2021-04-22' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- GVT's BDW regression fix for cmd parser (Zhenyu)
- Fix modesetting in case of unexpected AUX timeouts (Imre)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YIGZ3pQPgPQtZtyI@intel.com
parents b4d1913d 2d292995

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+2 −1
Original line number Diff line number Diff line
@@ -848,7 +848,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, 
	int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);



	if (lttpr_count < 0)

		return;

		/* Still continue with enabling the port and link training. */

		lttpr_count = 0;



	if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))

		intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);

drivers/gpu/drm/i915/gvt/cmd_parser.c

+13 −6
Original line number Diff line number Diff line
@@ -916,20 +916,27 @@ static int cmd_reg_handler(struct parser_exec_state *s, 


	if (!strncmp(cmd, "srm", 3) ||

			!strncmp(cmd, "lrm", 3)) {

		if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&

				offset != 0x21f0) {

		if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||

		    offset == 0x21f0 ||

		    (IS_BROADWELL(gvt->gt->i915) &&

		     offset == i915_mmio_reg_offset(INSTPM)))

			return 0;

		else {

			gvt_vgpu_err("%s access to register (%x)\n",

					cmd, offset);

			return -EPERM;

		} else

			return 0;

		}

	}



	if (!strncmp(cmd, "lrr-src", 7) ||

			!strncmp(cmd, "lrr-dst", 7)) {

		gvt_vgpu_err("not allowed cmd %s\n", cmd);

		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)

			return 0;

		else {

			gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);

			return -EPERM;

		}

	}



	if (!strncmp(cmd, "pipe_ctrl", 9)) {

		/* TODO: add LRI POST logic here */