Commit 2d292995 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-fixes-2021-04-20' of https://github.com/intel/gvt-linux into drm-intel-fixes 



gvt-fixes-2021-04-20

- Fix cmd parser regression on BDW (Zhenyu)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210420023312.GL1551@zhen-hp.sh.intel.com
parents d2b9935d 6b5b2a5b

drivers/gpu/drm/i915/gvt/cmd_parser.c

+13 −6
Original line number Diff line number Diff line
@@ -916,20 +916,27 @@ static int cmd_reg_handler(struct parser_exec_state *s, 


	if (!strncmp(cmd, "srm", 3) ||

			!strncmp(cmd, "lrm", 3)) {

		if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&

				offset != 0x21f0) {

		if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||

		    offset == 0x21f0 ||

		    (IS_BROADWELL(gvt->gt->i915) &&

		     offset == i915_mmio_reg_offset(INSTPM)))

			return 0;

		else {

			gvt_vgpu_err("%s access to register (%x)\n",

					cmd, offset);

			return -EPERM;

		} else

			return 0;

		}

	}



	if (!strncmp(cmd, "lrr-src", 7) ||

			!strncmp(cmd, "lrr-dst", 7)) {

		gvt_vgpu_err("not allowed cmd %s\n", cmd);

		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)

			return 0;

		else {

			gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);

			return -EPERM;

		}

	}



	if (!strncmp(cmd, "pipe_ctrl", 9)) {

		/* TODO: add LRI POST logic here */