Commit 6b5b2a5b authored by Zhenyu Wang's avatar Zhenyu Wang
Browse files

drm/i915/gvt: Fix BDW command parser regression 



On BDW new Windows driver has brought extra registers to handle for
LRM/LRR command in WA ctx. Add allowed registers in cmd parser for BDW.

Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Yan Zhao <yan.y.zhao@intel.com>
Cc: stable@vger.kernel.org
Tested-by: default avatarAlex Williamson <alex.williamson@redhat.com>
Reviewed-by: default avatarColin Xu <colin.xu@intel.com>
Fixes: 73a37a43 ("drm/i915/gvt: filter cmds "lrr-src" and "lrr-dst" in cmd_handler")
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210414084813.3763353-1-zhenyuw@linux.intel.com
parent b6a37a93

drivers/gpu/drm/i915/gvt/cmd_parser.c

+13 −6
Original line number Diff line number Diff line
@@ -916,20 +916,27 @@ static int cmd_reg_handler(struct parser_exec_state *s, 


	if (!strncmp(cmd, "srm", 3) ||

			!strncmp(cmd, "lrm", 3)) {

		if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&

				offset != 0x21f0) {

		if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||

		    offset == 0x21f0 ||

		    (IS_BROADWELL(gvt->gt->i915) &&

		     offset == i915_mmio_reg_offset(INSTPM)))

			return 0;

		else {

			gvt_vgpu_err("%s access to register (%x)\n",

					cmd, offset);

			return -EPERM;

		} else

			return 0;

		}

	}



	if (!strncmp(cmd, "lrr-src", 7) ||

			!strncmp(cmd, "lrr-dst", 7)) {

		gvt_vgpu_err("not allowed cmd %s\n", cmd);

		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)

			return 0;

		else {

			gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);

			return -EPERM;

		}

	}



	if (!strncmp(cmd, "pipe_ctrl", 9)) {

		/* TODO: add LRI POST logic here */