Commit b4d1913d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.12-2021-04-21' of... 

Merge tag 'amd-drm-fixes-5.12-2021-04-21' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.12-2021-04-21:

amdgpu:
- Fix gpuvm page table update issue
- Modifier fixes
- Register fix for dimgrey cavefish

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421220456.3839-1-alexander.deucher@amd.com
parents bf05bf16 24d03452

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+8 −2
Original line number Diff line number Diff line
@@ -3300,7 +3300,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 
	struct amdgpu_bo *root;

	uint64_t value, flags;

	struct amdgpu_vm *vm;

	long r;

	int r;



	spin_lock(&adev->vm_manager.pasid_lock);

	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
@@ -3349,6 +3349,12 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 
		value = 0;

	}



	r = dma_resv_reserve_shared(root->tbo.base.resv, 1);

	if (r) {

		pr_debug("failed %d to reserve fence slot\n", r);

		goto error_unlock;

	}



	r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,

					addr, flags, value, NULL, NULL,

					NULL);
@@ -3360,7 +3366,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 
error_unlock:

	amdgpu_bo_unreserve(root);

	if (r < 0)

		DRM_ERROR("Can't handle page fault (%ld)\n", r);

		DRM_ERROR("Can't handle page fault (%d)\n", r);



error_unref:

	amdgpu_bo_unref(&root);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −1
Original line number Diff line number Diff line
@@ -3280,7 +3280,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+6 −9
Original line number Diff line number Diff line
@@ -4071,13 +4071,6 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, 
	if (modifier == DRM_FORMAT_MOD_LINEAR)

		return true;



	/*

	 * The arbitrary tiling support for multiplane formats has not been hooked

	 * up.

	 */

	if (info->num_planes > 1)

		return false;



	/*

	 * For D swizzle the canonical modifier depends on the bpp, so check

	 * it here.
@@ -4096,6 +4089,10 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, 
		/* Per radeonsi comments 16/64 bpp are more complicated. */

		if (info->cpp[0] != 4)

			return false;

		/* We support multi-planar formats, but not when combined with

		 * additional DCC metadata planes. */

		if (info->num_planes > 1)

			return false;

	}



	return true;
@@ -4296,7 +4293,7 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev, 
		    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |

		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |

		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |

		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));

		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));



	add_modifier(mods, size, capacity, AMD_FMT_MOD |

		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
@@ -4308,7 +4305,7 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev, 
		    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |

		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |

		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |

		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));

		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));



	add_modifier(mods, size, capacity, AMD_FMT_MOD |

		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |