Commit 9a771038 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.18-tag2' of... 

Merge tag 'renesas-clk-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
   R-Car S4-8
 - A small fix

* tag 'renesas-clk-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779f0: Add PFC clock
  clk: renesas: r8a779f0: Add I2C clocks
  clk: renesas: r8a779f0: Add WDT clock
  clk: renesas: r8a779f0: Fix RSW2 clock divider
parents 80a6359f 73421f2a

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+17 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED("s0d12_hsc",	R8A779F0_CLK_S0D12_HSC,	CLK_S0,		12, 1),

	DEF_FIXED("cl16m_hsc",	R8A779F0_CLK_CL16M_HSC,	CLK_S0,		48, 1),

	DEF_FIXED("s0d2_cc",	R8A779F0_CLK_S0D2_CC,	CLK_S0,		2, 1),

	DEF_FIXED("rsw2",	R8A779F0_CLK_RSW2,	CLK_PLL5,	2, 1),

	DEF_FIXED("rsw2",	R8A779F0_CLK_RSW2,	CLK_PLL5_DIV2,	5, 1),

	DEF_FIXED("cbfusa",	R8A779F0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),
@@ -115,12 +115,24 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {

	DEF_MOD("i2c0",		518,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c1",		519,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c3",		521,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c4",		522,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c5",		523,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),

};



static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {

	MOD_CLK_ID(907),	/* WDT */

};



/*
@@ -177,6 +189,10 @@ const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { 
	.num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),

	.num_hw_mod_clks = 28 * 32,



	/* Critical Module Clocks */

	.crit_mod_clks = r8a779f0_crit_mod_clks,

	.num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks),



	/* Callbacks */

	.init = r8a779f0_cpg_mssr_init,

	.cpg_clk_register = rcar_gen4_cpg_clk_register,