Commit 80a6359f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.18-tag1' of... 

Merge tag 'renesas-clk-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
 - Add CAN-FD clocks on Renesas R-Car V3U
 - Add support for the new Renesas RZ/V2L SoC
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
  dt-bindings: clock: renesas: Document RZ/V2L SoC
  dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
  clk: renesas: r8a779a0: Add CANFD module clock
  clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
  clk: renesas: r8a7799[05]: Add MLP clocks
  clk: renesas: r8a779f0: Add SYS-DMAC clocks
parents e783362e a1bcf50a

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+8 −6
Original line number Diff line number Diff line
@@ -4,13 +4,13 @@ 
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode

title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module

  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.



  They provide the following functionalities:
@@ -22,7 +22,9 @@ description: | 


properties:

  compatible:

    const: renesas,r9a07g044-cpg  # RZ/G2{L,LC}

    enum:

      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg  # RZ/V2L



  reg:

    maxItems: 1
@@ -40,9 +42,9 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g044-cpg.h>

        <dt-bindings/clock/r9a07g*-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.

    const: 2



  '#power-domain-cells':
@@ -56,7 +58,7 @@ properties: 
  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g044-cpg.h>.

      the <dt-bindings/clock/r9a07g0*-cpg.h>.

    const: 1



required:

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ config CLK_RENESAS 
	select CLK_R8A779F0 if ARCH_R8A779F0

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_SH73A0 if ARCH_SH73A0



if CLK_RENESAS
@@ -163,6 +164,10 @@ config CLK_R9A07G044 
	bool "RZ/G2L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A07G054

	bool "RZ/V2L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_SH73A0

	bool "SH-Mobile AG5 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP
@@ -195,7 +200,7 @@ config CLK_RCAR_USB2_CLOCK_SEL 
	  This is a driver for R-Car USB2 clock selector



config CLK_RZG2L

	bool "Renesas RZ/G2L family clock support" if COMPILE_TEST

	bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



# Generic

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family

drivers/clk/renesas/r8a77990-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { 
	DEF_MOD("du0",			 724,	R8A77990_CLK_S1D1),

	DEF_MOD("lvds",			 727,	R8A77990_CLK_S2D1),



	DEF_MOD("mlp",			 802,	R8A77990_CLK_S2D1),

	DEF_MOD("vin5",			 806,	R8A77990_CLK_S1D2),

	DEF_MOD("vin4",			 807,	R8A77990_CLK_S1D2),

	DEF_MOD("etheravb",		 812,	R8A77990_CLK_S3D2),

drivers/clk/renesas/r8a77995-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { 
	DEF_MOD("du1",			 723,	R8A77995_CLK_S1D1),

	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),

	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),

	DEF_MOD("mlp",			 802,	R8A77995_CLK_S2D1),

	DEF_MOD("vin4",			 807,	R8A77995_CLK_S1D2),

	DEF_MOD("etheravb",		 812,	R8A77995_CLK_S3D2),

	DEF_MOD("imr0",			 823,	R8A77995_CLK_S1D2),