Commit a1bcf50a authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC 



The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.

Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take
care of the DRP-AI clocks/resets.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent fbf4ae93

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ config CLK_RENESAS 
	select CLK_R8A779F0 if ARCH_R8A779F0

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_SH73A0 if ARCH_SH73A0



if CLK_RENESAS
@@ -163,6 +164,10 @@ config CLK_R9A07G044 
	bool "RZ/G2L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A07G054

	bool "RZ/V2L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_SH73A0

	bool "SH-Mobile AG5 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP
@@ -195,7 +200,7 @@ config CLK_RCAR_USB2_CLOCK_SEL 
	  This is a driver for R-Car USB2 clock selector



config CLK_RZG2L

	bool "Renesas RZ/G2L family clock support" if COMPILE_TEST

	bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



# Generic

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family

drivers/clk/renesas/r9a07g044-cpg.c

+236 −190
Original line number Diff line number Diff line
@@ -11,12 +11,13 @@ 
#include <linux/kernel.h>



#include <dt-bindings/clock/r9a07g044-cpg.h>

#include <dt-bindings/clock/r9a07g054-cpg.h>



#include "rzg2l-cpg.h"



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,

	LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,



	/* External Input Clocks */

	CLK_EXTAL,
@@ -80,7 +81,13 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };



static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {

static const struct {

	struct cpg_core_clk common[44];

#ifdef CONFIG_CLK_R9A07G054

	struct cpg_core_clk drp[0];

#endif

} core_clks __initconst = {

	.common = {

		/* External Clock Inputs */

		DEF_INPUT("extal", CLK_EXTAL),
@@ -147,9 +154,20 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),

		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,

			CLK_DIVIDER_HIWORD_MASK),

	},

#ifdef CONFIG_CLK_R9A07G054

	.drp = {

	},

#endif

};



static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {

static const struct {

	struct rzg2l_mod_clk common[62];

#ifdef CONFIG_CLK_R9A07G054

	struct rzg2l_mod_clk drp[0];

#endif

} mod_clks = {

	.common = {

		DEF_MOD("gic",		R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,

					0x514, 0),

		DEF_MOD("ia55_pclk",	R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
@@ -274,6 +292,11 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
					0x5a8, 1),

		DEF_MOD("tsu_pclk",	R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,

					0x5ac, 0),

	},

#ifdef CONFIG_CLK_R9A07G054

	.drp = {

	},

#endif

};



static struct rzg2l_reset r9a07g044_resets[] = {
@@ -336,8 +359,8 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 


const struct rzg2l_cpg_info r9a07g044_cpg_info = {

	/* Core Clocks */

	.core_clks = r9a07g044_core_clks,

	.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),

	.core_clks = core_clks.common,

	.num_core_clks = ARRAY_SIZE(core_clks.common),

	.last_dt_core_clk = LAST_DT_CORE_CLK,

	.num_total_core_clks = MOD_CLK_BASE,
@@ -346,11 +369,34 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { 
	.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),



	/* Module Clocks */

	.mod_clks = r9a07g044_mod_clks,

	.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),

	.mod_clks = mod_clks.common,

	.num_mod_clks = ARRAY_SIZE(mod_clks.common),

	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,



	/* Resets */

	.resets = r9a07g044_resets,

	.num_resets = ARRAY_SIZE(r9a07g044_resets),

	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */

};



#ifdef CONFIG_CLK_R9A07G054

const struct rzg2l_cpg_info r9a07g054_cpg_info = {

	/* Core Clocks */

	.core_clks = core_clks.common,

	.num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp),

	.last_dt_core_clk = LAST_DT_CORE_CLK,

	.num_total_core_clks = MOD_CLK_BASE,



	/* Critical Module Clocks */

	.crit_mod_clks = r9a07g044_crit_mod_clks,

	.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),



	/* Module Clocks */

	.mod_clks = mod_clks.common,

	.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),

	.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,



	/* Resets */

	.resets = r9a07g044_resets,

	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */

};

#endif

drivers/clk/renesas/rzg2l-cpg.c

+6 −0
Original line number Diff line number Diff line
@@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { 
		.compatible = "renesas,r9a07g044-cpg",

		.data = &r9a07g044_cpg_info,

	},

#endif

#ifdef CONFIG_CLK_R9A07G054

	{

		.compatible = "renesas,r9a07g054-cpg",

		.data = &r9a07g054_cpg_info,

	},

#endif

	{ /* sentinel */ }

};

drivers/clk/renesas/rzg2l-cpg.h

+1 −0
Original line number Diff line number Diff line
@@ -203,5 +203,6 @@ struct rzg2l_cpg_info { 
};



extern const struct rzg2l_cpg_info r9a07g044_cpg_info;

extern const struct rzg2l_cpg_info r9a07g054_cpg_info;



#endif