Commit 945409a6 authored by Catalin Marinas's avatar Catalin Marinas
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Merge branches 'for-next/misc', 'for-next/cache-ops-dzp',... 

Merge branches 'for-next/misc', 'for-next/cache-ops-dzp', 'for-next/stacktrace', 'for-next/xor-neon', 'for-next/kasan', 'for-next/armv8_7-fp', 'for-next/atomics', 'for-next/bti', 'for-next/sve', 'for-next/kselftest' and 'for-next/kcsan', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf: (32 commits)
  arm64: perf: Don't register user access sysctl handler multiple times
  drivers: perf: marvell_cn10k: fix an IS_ERR() vs NULL check
  perf/smmuv3: Fix unused variable warning when CONFIG_OF=n
  arm64: perf: Support new DT compatibles
  arm64: perf: Simplify registration boilerplate
  arm64: perf: Support Denver and Carmel PMUs
  drivers/perf: hisi: Add driver for HiSilicon PCIe PMU
  docs: perf: Add description for HiSilicon PCIe PMU driver
  dt-bindings: perf: Add YAML schemas for Marvell CN10K LLC-TAD pmu bindings
  drivers: perf: Add LLC-TAD perf counter support
  perf/smmuv3: Synthesize IIDR from CoreSight ID registers
  perf/smmuv3: Add devicetree support
  dt-bindings: Add Arm SMMUv3 PMCG binding
  perf/arm-cmn: Add debugfs topology info
  perf/arm-cmn: Add CI-700 Support
  dt-bindings: perf: arm-cmn: Add CI-700
  perf/arm-cmn: Support new IP features
  perf/arm-cmn: Demarcate CMN-600 specifics
  perf/arm-cmn: Move group validation data off-stack
  perf/arm-cmn: Optimise DTC counter accesses
  ...

* for-next/misc:
  : Miscellaneous patches
  arm64: Use correct method to calculate nomap region boundaries
  arm64: Drop outdated links in comments
  arm64: errata: Fix exec handling in erratum 1418040 workaround
  arm64: Unhash early pointer print plus improve comment
  asm-generic: introduce io_stop_wc() and add implementation for ARM64
  arm64: remove __dma_*_area() aliases
  docs/arm64: delete a space from tagged-address-abi
  arm64/fp: Add comments documenting the usage of state restore functions
  arm64: mm: Use asid feature macro for cheanup
  arm64: mm: Rename asid2idx() to ctxid2asid()
  arm64: kexec: reduce calls to page_address()
  arm64: extable: remove unused ex_handler_t definition
  arm64: entry: Use SDEI event constants
  arm64: Simplify checking for populated DT
  arm64/kvm: Fix bitrotted comment for SVE handling in handle_exit.c

* for-next/cache-ops-dzp:
  : Avoid DC instructions when DCZID_EL0.DZP == 1
  arm64: mte: DC {GVA,GZVA} shouldn't be used when DCZID_EL0.DZP == 1
  arm64: clear_page() shouldn't use DC ZVA when DCZID_EL0.DZP == 1

* for-next/stacktrace:
  : Unify the arm64 unwind code
  arm64: Make some stacktrace functions private
  arm64: Make dump_backtrace() use arch_stack_walk()
  arm64: Make profile_pc() use arch_stack_walk()
  arm64: Make return_address() use arch_stack_walk()
  arm64: Make __get_wchan() use arch_stack_walk()
  arm64: Make perf_callchain_kernel() use arch_stack_walk()
  arm64: Mark __switch_to() as __sched
  arm64: Add comment for stack_info::kr_cur
  arch: Make ARCH_STACKWALK independent of STACKTRACE

* for-next/xor-neon:
  : Use SHA3 instructions to speed up XOR
  arm64/xor: use EOR3 instructions when available

* for-next/kasan:
  : Log potential KASAN shadow aliases
  arm64: mm: log potential KASAN shadow alias
  arm64: mm: use die_kernel_fault() in do_mem_abort()

* for-next/armv8_7-fp:
  : Add HWCAPS for ARMv8.7 FEAT_AFP amd FEAT_RPRES
  arm64: cpufeature: add HWCAP for FEAT_RPRES
  arm64: add ID_AA64ISAR2_EL1 sys register
  arm64: cpufeature: add HWCAP for FEAT_AFP

* for-next/atomics:
  : arm64 atomics clean-ups and codegen improvements
  arm64: atomics: lse: define RETURN ops in terms of FETCH ops
  arm64: atomics: lse: improve constraints for simple ops
  arm64: atomics: lse: define ANDs in terms of ANDNOTs
  arm64: atomics lse: define SUBs in terms of ADDs
  arm64: atomics: format whitespace consistently

* for-next/bti:
  : BTI clean-ups
  arm64: Ensure that the 'bti' macro is defined where linkage.h is included
  arm64: Use BTI C directly and unconditionally
  arm64: Unconditionally override SYM_FUNC macros
  arm64: Add macro version of the BTI instruction
  arm64: ftrace: add missing BTIs
  arm64: kexec: use __pa_symbol(empty_zero_page)
  arm64: update PAC description for kernel

* for-next/sve:
  : SVE code clean-ups and refactoring in prepararation of Scalable Matrix Extensions
  arm64/sve: Minor clarification of ABI documentation
  arm64/sve: Generalise vector length configuration prctl() for SME
  arm64/sve: Make sysctl interface for SVE reusable by SME

* for-next/kselftest:
  : arm64 kselftest additions
  kselftest/arm64: Add pidbench for floating point syscall cases
  kselftest/arm64: Add a test program to exercise the syscall ABI
  kselftest/arm64: Allow signal tests to trigger from a function
  kselftest/arm64: Parameterise ptrace vector length information

* for-next/kcsan:
  : Enable KCSAN for arm64
  arm64: Enable KCSAN
parents 3da4390b daa149dd 685e2564 d2d1d264 2c54b423 07b742a4 1175011a 053f58ba dd73d18e aed34d9e 2c94ebed dd03762a

Documentation/arm64/cpu-feature-registers.rst

+17 −0
Original line number Diff line number Diff line
@@ -275,6 +275,23 @@ infrastructure: 
     | SVEVer                       | [3-0]   |    y    |

     +------------------------------+---------+---------+



  8) ID_AA64MMFR1_EL1 - Memory model feature register 1



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | AFP                          | [47-44] |    y    |

     +------------------------------+---------+---------+



  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | RPRES                        | [7-4]   |    y    |

     +------------------------------+---------+---------+





Appendix I: Example

-------------------

Documentation/arm64/elf_hwcaps.rst

+8 −0
Original line number Diff line number Diff line
@@ -251,6 +251,14 @@ HWCAP2_ECV 


    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.



HWCAP2_AFP



    Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.



HWCAP2_RPRES



    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

Documentation/arm64/pointer-authentication.rst

+4 −5
Original line number Diff line number Diff line
@@ -53,11 +53,10 @@ The number of bits that the PAC occupies in a pointer is 55 minus the 
virtual address size configured by the kernel. For example, with a

virtual address size of 48, the PAC is 7 bits wide.



Recent versions of GCC can compile code with APIAKey-based return

address protection when passed the -msign-return-address option. This

uses instructions in the HINT space (unless -march=armv8.3-a or higher

is also passed), and such code can run on systems without the pointer

authentication extension.

When ARM64_PTR_AUTH_KERNEL is selected, the kernel will be compiled

with HINT space pointer authentication instructions protecting

function returns. Kernels built with this option will work on hardware

with or without pointer authentication support.



In addition to exec(), keys can also be reinitialized to random values

using the PR_PAC_RESET_KEYS prctl. A bitmask of PR_PAC_APIAKEY,

Documentation/arm64/sve.rst

+1 −1
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ prctl(PR_SVE_GET_VL) 
    vector length change (which would only normally be the case between a

    fork() or vfork() and the corresponding execve() in typical use).



    To extract the vector length from the result, and it with

    To extract the vector length from the result, bitwise and it with

    PR_SVE_VL_LEN_MASK.



    Return value: a nonnegative value on success, or a negative value on error:

Documentation/memory-barriers.txt

+8 −0
Original line number Diff line number Diff line
@@ -1950,6 +1950,14 @@ There are some more advanced barrier functions: 
     For load from persistent memory, existing read memory barriers are sufficient

     to ensure read ordering.



 (*) io_stop_wc();



     For memory accesses with write-combining attributes (e.g. those returned

     by ioremap_wc(), the CPU may wait for prior accesses to be merged with

     subsequent ones. io_stop_wc() can be used to prevent the merging of

     write-combining memory accesses before this macro with those after it when

     such wait has performance implications.



===============================

IMPLICIT KERNEL MEMORY BARRIERS

===============================