Commit 1175011a authored by Joey Gouly's avatar Joey Gouly Committed by Catalin Marinas
Browse files

arm64: cpufeature: add HWCAP for FEAT_RPRES



Add a new HWCAP to detect the Increased precision of Reciprocal Estimate
and Reciprocal Square Root Estimate feature (FEAT_RPRES), introduced in Armv8.7.

Also expose this to userspace in the ID_AA64ISAR2_EL1 feature register.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211210165432.8106-4-joey.gouly@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 9e45365f
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+8 −0
Original line number Diff line number Diff line
@@ -283,6 +283,14 @@ infrastructure:
     | AFP                          | [47-44] |    y    |
     +------------------------------+---------+---------+

  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2

     +------------------------------+---------+---------+
     | Name                         |  bits   | visible |
     +------------------------------+---------+---------+
     | RPRES                        | [7-4]   |    y    |
     +------------------------------+---------+---------+


Appendix I: Example
-------------------
+4 −0
Original line number Diff line number Diff line
@@ -255,6 +255,10 @@ HWCAP2_AFP

    Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.

HWCAP2_RPRES

    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.

4. Unused AT_HWCAP bits
-----------------------

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@
#define KERNEL_HWCAP_MTE		__khwcap2_feature(MTE)
#define KERNEL_HWCAP_ECV		__khwcap2_feature(ECV)
#define KERNEL_HWCAP_AFP		__khwcap2_feature(AFP)
#define KERNEL_HWCAP_RPRES		__khwcap2_feature(RPRES)

/*
 * This yields a mask that user programs can use to figure out what
+1 −0
Original line number Diff line number Diff line
@@ -77,5 +77,6 @@
#define HWCAP2_MTE		(1 << 18)
#define HWCAP2_ECV		(1 << 19)
#define HWCAP2_AFP		(1 << 20)
#define HWCAP2_RPRES		(1 << 21)

#endif /* _UAPI__ASM_HWCAP_H */
+2 −0
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@@ -226,6 +226,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
};

static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
	ARM64_FTR_END,
};

@@ -2487,6 +2488,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
#endif /* CONFIG_ARM64_MTE */
	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
	{},
};

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