Commit 622909e5 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/mte', 'for-next/misc' and 'for-next/kselftest',... 

Merge branches 'for-next/mte', 'for-next/misc' and 'for-next/kselftest', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf:
  arm64/perf: Replace '0xf' instances with ID_AA64DFR0_PMUVER_IMP_DEF

* for-next/mte:
  : Miscellaneous MTE improvements.
  arm64/cpufeature: Optionally disable MTE via command-line
  arm64: kasan: mte: remove redundant mte_report_once logic
  arm64: kasan: mte: use a constant kernel GCR_EL1 value
  arm64: avoid double ISB on kernel entry
  arm64: mte: optimize GCR_EL1 modification on kernel entry/exit
  Documentation: document the preferred tag checking mode feature
  arm64: mte: introduce a per-CPU tag checking mode preference
  arm64: move preemption disablement to prctl handlers
  arm64: mte: change ASYNC and SYNC TCF settings into bitfields
  arm64: mte: rename gcr_user_excl to mte_ctrl
  arm64: mte: avoid TFSRE0_EL1 related operations unless in async mode

* for-next/misc:
  : Miscellaneous updates.
  arm64: Do not trap PMSNEVFR_EL1
  arm64: mm: fix comment typo of pud_offset_phys()
  arm64: signal32: Drop pointless call to sigdelsetmask()
  arm64/sve: Better handle failure to allocate SVE register storage
  arm64: Document the requirement for SCR_EL3.HCE
  arm64: head: avoid over-mapping in map_memory
  arm64/sve: Add a comment documenting the binutils needed for SVE asm
  arm64/sve: Add some comments for sve_save/load_state()
  arm64: replace in_irq() with in_hardirq()
  arm64: mm: Fix TLBI vs ASID rollover
  arm64: entry: Add SYM_CODE annotation for __bad_stack
  arm64: fix typo in a comment
  arm64: move the (z)install rules to arch/arm64/Makefile
  arm64/sve: Make fpsimd_bind_task_to_cpu() static
  arm64: unnecessary end 'return;' in void functions
  arm64/sme: Document boot requirements for SME
  arm64: use __func__ to get function name in pr_err
  arm64: SSBS/DIT: print SSBS and DIT bit when printing PSTATE
  arm64: cpufeature: Use defined macro instead of magic numbers
  arm64/kexec: Test page size support with new TGRAN range values

* for-next/kselftest:
  : Kselftest additions for arm64.
  kselftest/arm64: signal: Add a TODO list for signal handling tests
  kselftest/arm64: signal: Add test case for SVE register state in signals
  kselftest/arm64: signal: Verify that signals can't change the SVE vector length
  kselftest/arm64: signal: Check SVE signal frame shows expected vector length
  kselftest/arm64: signal: Support signal frames with SVE register data
  kselftest/arm64: signal: Add SVE to the set of features we can check for
  kselftest/arm64: pac: Fix skipping of tests on systems without PAC
  kselftest/arm64: mte: Fix misleading output when skipping tests
  kselftest/arm64: Add a TODO list for floating point tests
  kselftest/arm64: Add tests for SVE vector configuration
  kselftest/arm64: Validate vector lengths are set in sve-probe-vls
  kselftest/arm64: Provide a helper binary and "library" for SVE RDVL
  kselftest/arm64: Ignore check_gcr_el1_cswitch binary
parents fd264b31 7a062ce3 50cb99fa fa5ca80d

Documentation/ABI/testing/sysfs-devices-system-cpu

+17 −0
Original line number Diff line number Diff line
@@ -640,3 +640,20 @@ Description: SPURR ticks for cpuX when it was idle. 


		This sysfs interface exposes the number of SPURR ticks

		for cpuX when it was idle.



What: 		/sys/devices/system/cpu/cpuX/mte_tcf_preferred

Date:		July 2021

Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>

Description:	Preferred MTE tag checking mode



		When a user program specifies more than one MTE tag checking

		mode, this sysfs node is used to specify which mode should

		be preferred when scheduling a task on that CPU. Possible

		values:



		================  ==============================================

		"sync"	  	  Prefer synchronous mode

		"async"	  	  Prefer asynchronous mode

		================  ==============================================



		See also: Documentation/arm64/memory-tagging-extension.rst

Documentation/admin-guide/kernel-parameters.txt

+3 −0
Original line number Diff line number Diff line
@@ -380,6 +380,9 @@ 
	arm64.nopauth	[ARM64] Unconditionally disable Pointer Authentication

			support



	arm64.nomte	[ARM64] Unconditionally disable Memory Tagging Extension

			support



	ataflop=	[HW,M68k]



	atarimouse=	[HW,MOUSE] Atari Mouse

Documentation/arm64/booting.rst

+33 −4
Original line number Diff line number Diff line
@@ -207,11 +207,18 @@ Before jumping into the kernel, the following conditions must be met: 
  software at a higher exception level to prevent execution in an UNKNOWN

  state.



  For all systems:

  - If EL3 is present:



    - SCR_EL3.FIQ must have the same value across all CPUs the kernel is

      executing on.

    - The value of SCR_EL3.FIQ must be the same as the one present at boot

      time whenever the kernel is executing.



  - If EL3 is present and the kernel is entered at EL2:



    - SCR_EL3.HCE (bit 8) must be initialised to 0b1.



  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:
@@ -311,6 +318,28 @@ Before jumping into the kernel, the following conditions must be met: 
    - ZCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



  For CPUs with the Scalable Matrix Extension (FEAT_SME):



  - If EL3 is present:



    - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.



    - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.



    - SMCR_EL3.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



 - If the kernel is entered at EL1 and EL2 is present:



    - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.



    - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.



    - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.



    - SMCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.  Where the values documented

Documentation/arm64/memory-tagging-extension.rst

+41 −7
Original line number Diff line number Diff line
@@ -77,14 +77,20 @@ configurable behaviours: 
  address is unknown).



The user can select the above modes, per thread, using the

``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where

``flags`` contain one of the following values in the ``PR_MTE_TCF_MASK``

``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where ``flags``

contains any number of the following values in the ``PR_MTE_TCF_MASK``

bit-field:



- ``PR_MTE_TCF_NONE``  - *Ignore* tag check faults

- ``PR_MTE_TCF_NONE``  - *Ignore* tag check faults

                         (ignored if combined with other options)

- ``PR_MTE_TCF_SYNC``  - *Synchronous* tag check fault mode

- ``PR_MTE_TCF_ASYNC`` - *Asynchronous* tag check fault mode



If no modes are specified, tag check faults are ignored. If a single

mode is specified, the program will run in that mode. If multiple

modes are specified, the mode is selected as described in the "Per-CPU

preferred tag checking modes" section below.



The current tag check fault mode can be read using the

``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call.
@@ -120,13 +126,39 @@ in the ``PR_MTE_TAG_MASK`` bit-field. 
interface provides an include mask. An include mask of ``0`` (exclusion

mask ``0xffff``) results in the CPU always generating tag ``0``.



Per-CPU preferred tag checking mode

-----------------------------------



On some CPUs the performance of MTE in stricter tag checking modes

is similar to that of less strict tag checking modes. This makes it

worthwhile to enable stricter checks on those CPUs when a less strict

checking mode is requested, in order to gain the error detection

benefits of the stricter checks without the performance downsides. To

support this scenario, a privileged user may configure a stricter

tag checking mode as the CPU's preferred tag checking mode.



The preferred tag checking mode for each CPU is controlled by

``/sys/devices/system/cpu/cpu<N>/mte_tcf_preferred``, to which a

privileged user may write the value ``async`` or ``sync``.  The default

preferred mode for each CPU is ``async``.



To allow a program to potentially run in the CPU's preferred tag

checking mode, the user program may set multiple tag check fault mode

bits in the ``flags`` argument to the ``prctl(PR_SET_TAGGED_ADDR_CTRL,

flags, 0, 0, 0)`` system call. If the CPU's preferred tag checking

mode is in the task's set of provided tag checking modes (this will

always be the case at present because the kernel only supports two

tag checking modes, but future kernels may support more modes), that

mode will be selected. Otherwise, one of the modes in the task's mode

set will be selected in a currently unspecified manner.



Initial process state

---------------------



On ``execve()``, the new process has the following configuration:



- ``PR_TAGGED_ADDR_ENABLE`` set to 0 (disabled)

- Tag checking mode set to ``PR_MTE_TCF_NONE``

- No tag checking modes are selected (tag check faults ignored)

- ``PR_MTE_TAG_MASK`` set to 0 (all tags excluded)

- ``PSTATE.TCO`` set to 0

- ``PROT_MTE`` not set on any of the initial memory maps
@@ -251,11 +283,13 @@ Example of correct usage 
                    return EXIT_FAILURE;



            /*

             * Enable the tagged address ABI, synchronous MTE tag check faults and

             * allow all non-zero tags in the randomly generated set.

             * Enable the tagged address ABI, synchronous or asynchronous MTE

             * tag check faults (based on per-CPU preference) and allow all

             * non-zero tags in the randomly generated set.

             */

            if (prctl(PR_SET_TAGGED_ADDR_CTRL,

                      PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | (0xfffe << PR_MTE_TAG_SHIFT),

                      PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC |

                      (0xfffe << PR_MTE_TAG_SHIFT),

                      0, 0, 0)) {

                    perror("prctl() failed");

                    return EXIT_FAILURE;

arch/arm64/Makefile

+5 −2
Original line number Diff line number Diff line
@@ -165,8 +165,11 @@ Image: vmlinux 
Image.%: Image

	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@



zinstall install:

	$(Q)$(MAKE) $(build)=$(boot) $@

install: install-image := Image

zinstall: install-image := Image.gz

install zinstall:

	$(CONFIG_SHELL) $(srctree)/$(boot)/install.sh $(KERNELRELEASE) \

	$(boot)/$(install-image) System.map "$(INSTALL_PATH)"



PHONY += vdso_install

vdso_install: