Commit 50cb99fa authored by Alexandru Elisei's avatar Alexandru Elisei Committed by Catalin Marinas
Browse files

arm64: Do not trap PMSNEVFR_EL1 



Commit 31c00d2a ("arm64: Disable fine grained traps on boot") zeroed
the fine grained trap registers to prevent unwanted register traps from
occuring. However, for the PMSNEVFR_EL1 register, the corresponding
HDFG{R,W}TR_EL2.nPMSNEVFR_EL1 fields must be 1 to disable trapping. Set
both fields to 1 if FEAT_SPEv1p2 is detected to disable read and write
traps.

Fixes: 31c00d2a ("arm64: Disable fine grained traps on boot")
Cc: <stable@vger.kernel.org> # 5.13.x
Signed-off-by: default avatarAlexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210824154523.906270-1-alexandru.elisei@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 5845e703

arch/arm64/include/asm/el2_setup.h

+11 −2
Original line number Diff line number Diff line
@@ -150,8 +150,17 @@ 
	ubfx	x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4

	cbz	x1, .Lskip_fgt_\@



	msr_s	SYS_HDFGRTR_EL2, xzr

	msr_s	SYS_HDFGWTR_EL2, xzr

	mov	x0, xzr

	mrs	x1, id_aa64dfr0_el1

	ubfx	x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4

	cmp	x1, #3

	b.lt	.Lset_fgt_\@

	/* Disable PMSNEVFR_EL1 read and write traps */

	orr	x0, x0, #(1 << 62)



.Lset_fgt_\@:

	msr_s	SYS_HDFGRTR_EL2, x0

	msr_s	SYS_HDFGWTR_EL2, x0

	msr_s	SYS_HFGRTR_EL2, xzr

	msr_s	SYS_HFGWTR_EL2, xzr

	msr_s	SYS_HFGITR_EL2, xzr