Commit 60950df7 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' and...

Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' and 'clk-core' into clk-next

 - Various cleanups and improvements to Mediatek clk drivers to reduce
   code size and modernize the drivers
 - Support for Mediatek MT7891 SoC clks

* clk-microchip:
  clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60
  clk: at91: mark ddr clocks as critical

* clk-allwinner:
  clk: sunxi-ng: d1: Add CAN bus gates and resets
  dt-bindings: clock: Add D1 CAN bus gates and resets
  clk: sunxi-ng: d1: Mark cpux clock as critical
  clk: sunxi-ng: d1: Allow building for R528/T113
  clk: sunxi-ng: Move SoC driver conditions to dependencies
  clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies
  clk: sunxi-ng: Avoid computing the rate twice
  clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock
  clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues

* clk-mediatek: (29 commits)
  clk: mediatek: clk-mtk: Remove unneeded semicolon
  clk: mediatek: remove MT8195 vppsys/0/1 simple_probe
  dt-bindings: arm: mediatek: migrate MT8195 vppsys0/1 to mtk-mmsys driver
  clk: mediatek: add MT7981 clock support
  dt-bindings: clock: mediatek: add mt7981 clock IDs
  dt-bindings: clock: Add compatibles for MT7981
  clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe()
  clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled
  clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe()
  clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe()
  clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe()
  clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe()
  clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs
  clk: mediatek: mt8186: Join top_adj_div and top_muxes
  clk: mediatek: mt8192: Join top_adj_divs and top_muxes
  clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs
  clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe()
  clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
  clk: mediatek: Switch to mtk_clk_simple_probe() where possible
  clk: mediatek: mt8173: Break down clock drivers and allow module build
  ...

* clk-imx:
  clk: imx: pll14xx: fix recalc_rate for negative kdiv
  MAINTAINERS: clk: imx: Add Peng Fan as reviewer
  clk: imx: fix compile testing imxrt1050
  clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static
  clk: imx6ul: add ethernet refclock mux support
  clk: imx6ul: fix enet1 gate configuration
  clk: imx: add imx_obtain_fixed_of_clock()
  clk: imx6q: add ethernet refclock mux support
  clk: imx: add clk-gpr-mux driver
  dt-bindings: imx8ulp: clock: no spaces before tabs
  clk: imx6sll: add proper spdx license identifier
  clk: imx: imx93: invoke imx_register_uart_clocks
  clk: imx: remove clk_count of imx_register_uart_clocks
  clk: imx: get stdout clk count from device tree
  clk: imx: avoid memory leak

* clk-core:
  clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()
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+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required Properties:
	- "mediatek,mt7622-ethsys", "syscon"
	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
	- "mediatek,mt7629-ethsys", "syscon"
	- "mediatek,mt7981-ethsys", "syscon"
	- "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties:
              - mediatek,mt6797-infracfg
              - mediatek,mt7622-infracfg
              - mediatek,mt7629-infracfg
              - mediatek,mt7981-infracfg
              - mediatek,mt7986-infracfg
              - mediatek,mt8135-infracfg
              - mediatek,mt8167-infracfg
+0 −16
Original line number Diff line number Diff line
@@ -28,11 +28,9 @@ properties:
          - mediatek,mt8195-imp_iic_wrap_s
          - mediatek,mt8195-imp_iic_wrap_w
          - mediatek,mt8195-mfgcfg
          - mediatek,mt8195-vppsys0
          - mediatek,mt8195-wpesys
          - mediatek,mt8195-wpesys_vpp0
          - mediatek,mt8195-wpesys_vpp1
          - mediatek,mt8195-vppsys1
          - mediatek,mt8195-imgsys
          - mediatek,mt8195-imgsys1_dip_top
          - mediatek,mt8195-imgsys1_dip_nr
@@ -92,13 +90,6 @@ examples:
        #clock-cells = <1>;
    };

  - |
    vppsys0: clock-controller@14000000 {
        compatible = "mediatek,mt8195-vppsys0";
        reg = <0x14000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    wpesys: clock-controller@14e00000 {
        compatible = "mediatek,mt8195-wpesys";
@@ -120,13 +111,6 @@ examples:
        #clock-cells = <1>;
    };

  - |
    vppsys1: clock-controller@14f00000 {
        compatible = "mediatek,mt8195-vppsys1";
        reg = <0x14f00000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys: clock-controller@15000000 {
        compatible = "mediatek,mt8195-imgsys";
+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ Required Properties:
- compatible: Should be:
	- "mediatek,mt7622-sgmiisys", "syscon"
	- "mediatek,mt7629-sgmiisys", "syscon"
	- "mediatek,mt7981-sgmiisys_0", "syscon"
	- "mediatek,mt7981-sgmiisys_1", "syscon"
	- "mediatek,mt7986-sgmiisys_0", "syscon"
	- "mediatek,mt7986-sgmiisys_1", "syscon"
- #clock-cells: Must be 1
+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties:
      - enum:
          - mediatek,mt6797-apmixedsys
          - mediatek,mt7622-apmixedsys
          - mediatek,mt7981-apmixedsys
          - mediatek,mt7986-apmixedsys
          - mediatek,mt8135-apmixedsys
          - mediatek,mt8173-apmixedsys
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