Commit 633ff554 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-6.3-1' of... 

Merge tag 'sunxi-clk-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Jernej Skrabec:

 - add D1 CAN bus gates and resets
 - mark D1 CPUX clock as critical
 - reuse D1 driver for R528/T113
 - cleanup sunxi-ng kconfig
 - fix sunxi-ng kernel-doc issues
 - model H3/H5 DRAM clock as fixed clock

* tag 'sunxi-clk-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: d1: Add CAN bus gates and resets
  dt-bindings: clock: Add D1 CAN bus gates and resets
  clk: sunxi-ng: d1: Mark cpux clock as critical
  clk: sunxi-ng: d1: Allow building for R528/T113
  clk: sunxi-ng: Move SoC driver conditions to dependencies
  clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies
  clk: sunxi-ng: Avoid computing the rate twice
  clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock
  clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues
parents 1b929c02 e6f2ffea

drivers/clk/sunxi-ng/Kconfig

+36 −35
Original line number Diff line number Diff line
@@ -9,112 +9,113 @@ if SUNXI_CCU 


config SUNIV_F1C100S_CCU

	tristate "Support for the Allwinner newer F1C100s CCU"

	default MACH_SUNIV

	default y

	depends on MACH_SUNIV || COMPILE_TEST



config SUN20I_D1_CCU

	tristate "Support for the Allwinner D1 CCU"

	default RISCV && ARCH_SUNXI

	depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST

	tristate "Support for the Allwinner D1/R528/T113 CCU"

	default y

	depends on MACH_SUN8I || RISCV || COMPILE_TEST



config SUN20I_D1_R_CCU

	tristate "Support for the Allwinner D1 PRCM CCU"

	default RISCV && ARCH_SUNXI

	depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST

	tristate "Support for the Allwinner D1/R528/T113 PRCM CCU"

	default y

	depends on MACH_SUN8I || RISCV || COMPILE_TEST



config SUN50I_A64_CCU

	tristate "Support for the Allwinner A64 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on ARM64 || COMPILE_TEST



config SUN50I_A100_CCU

	tristate "Support for the Allwinner A100 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on ARM64 || COMPILE_TEST



config SUN50I_A100_R_CCU

	tristate "Support for the Allwinner A100 PRCM CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on ARM64 || COMPILE_TEST



config SUN50I_H6_CCU

	tristate "Support for the Allwinner H6 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on ARM64 || COMPILE_TEST



config SUN50I_H616_CCU

	tristate "Support for the Allwinner H616 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on ARM64 || COMPILE_TEST



config SUN50I_H6_R_CCU

	tristate "Support for the Allwinner H6 and H616 PRCM CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on ARM64 || COMPILE_TEST



config SUN4I_A10_CCU

	tristate "Support for the Allwinner A10/A20 CCU"

	default MACH_SUN4I

	default MACH_SUN7I

	default y

	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST



config SUN5I_CCU

	bool "Support for the Allwinner sun5i family CCM"

	default MACH_SUN5I

	default y

	depends on MACH_SUN5I || COMPILE_TEST

	depends on SUNXI_CCU=y



config SUN6I_A31_CCU

	tristate "Support for the Allwinner A31/A31s CCU"

	default MACH_SUN6I

	default y

	depends on MACH_SUN6I || COMPILE_TEST



config SUN6I_RTC_CCU

	tristate "Support for the Allwinner H616/R329 RTC CCU"

	default ARCH_SUNXI

	depends on ARCH_SUNXI || COMPILE_TEST

	default y

	depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST



config SUN8I_A23_CCU

	tristate "Support for the Allwinner A23 CCU"

	default MACH_SUN8I

	default y

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_A33_CCU

	tristate "Support for the Allwinner A33 CCU"

	default MACH_SUN8I

	default y

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_A83T_CCU

	tristate "Support for the Allwinner A83T CCU"

	default MACH_SUN8I

	default y

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_H3_CCU

	tristate "Support for the Allwinner H3 CCU"

	default MACH_SUN8I || (ARM64 && ARCH_SUNXI)

	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	default y

	depends on MACH_SUN8I || ARM64 || COMPILE_TEST



config SUN8I_V3S_CCU

	tristate "Support for the Allwinner V3s CCU"

	default MACH_SUN8I

	default y

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_DE2_CCU

	tristate "Support for the Allwinner SoCs DE2 CCU"

	default MACH_SUN8I || (ARM64 && ARCH_SUNXI)

	default y

	depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST



config SUN8I_R40_CCU

	tristate "Support for the Allwinner R40 CCU"

	default MACH_SUN8I

	default y

	depends on MACH_SUN8I || COMPILE_TEST



config SUN9I_A80_CCU

	tristate "Support for the Allwinner A80 CCU"

	default MACH_SUN9I

	default y

	depends on MACH_SUN9I || COMPILE_TEST



config SUN8I_R_CCU

	tristate "Support for Allwinner SoCs' PRCM CCUs"

	default MACH_SUN8I || (ARCH_SUNXI && ARM64)

	default y

	depends on MACH_SUN8I || ARM64 || COMPILE_TEST



endif

drivers/clk/sunxi-ng/ccu-sun20i-d1.c

+12 −1
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ static const struct clk_parent_data cpux_parents[] = { 
	{ .hw = &pll_periph0_800M_clk.common.hw },

};

static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,

			  0x500, 24, 3, CLK_SET_RATE_PARENT);

			  0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);



static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };

static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
@@ -469,6 +469,11 @@ static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 
static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,

			  0x91c, BIT(3), 0);



static SUNXI_CCU_GATE_HWS(bus_can0_clk, "bus-can0", apb1_hws,

			  0x92c, BIT(0), 0);

static SUNXI_CCU_GATE_HWS(bus_can1_clk, "bus-can1", apb1_hws,

			  0x92c, BIT(1), 0);



static const struct clk_parent_data spi_parents[] = {

	{ .fw_name = "hosc" },

	{ .hw = &pll_periph0_clk.hw },
@@ -997,6 +1002,8 @@ static struct ccu_common *sun20i_d1_ccu_clks[] = { 
	&bus_i2c1_clk.common,

	&bus_i2c2_clk.common,

	&bus_i2c3_clk.common,

	&bus_can0_clk.common,

	&bus_can1_clk.common,

	&spi0_clk.common,

	&spi1_clk.common,

	&bus_spi0_clk.common,
@@ -1147,6 +1154,8 @@ static struct clk_hw_onecell_data sun20i_d1_hw_clks = { 
		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,

		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,

		[CLK_BUS_I2C3]		= &bus_i2c3_clk.common.hw,

		[CLK_BUS_CAN0]		= &bus_can0_clk.common.hw,

		[CLK_BUS_CAN1]		= &bus_can1_clk.common.hw,

		[CLK_SPI0]		= &spi0_clk.common.hw,

		[CLK_SPI1]		= &spi1_clk.common.hw,

		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
@@ -1252,6 +1261,8 @@ static struct ccu_reset_map sun20i_d1_ccu_resets[] = { 
	[RST_BUS_I2C1]		= { 0x91c, BIT(17) },

	[RST_BUS_I2C2]		= { 0x91c, BIT(18) },

	[RST_BUS_I2C3]		= { 0x91c, BIT(19) },

	[RST_BUS_CAN0]		= { 0x92c, BIT(16) },

	[RST_BUS_CAN1]		= { 0x92c, BIT(17) },

	[RST_BUS_SPI0]		= { 0x96c, BIT(16) },

	[RST_BUS_SPI1]		= { 0x96c, BIT(17) },

	[RST_BUS_EMAC]		= { 0x97c, BIT(16) },

drivers/clk/sunxi-ng/ccu-sun20i-d1.h

+1 −1
Original line number Diff line number Diff line
@@ -10,6 +10,6 @@ 
#include <dt-bindings/clock/sun20i-d1-ccu.h>

#include <dt-bindings/reset/sun20i-d1-ccu.h>



#define CLK_NUMBER		(CLK_FANOUT2 + 1)

#define CLK_NUMBER		(CLK_BUS_CAN1 + 1)



#endif /* _CCU_SUN20I_D1_H_ */

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+10 −5
Original line number Diff line number Diff line
@@ -434,8 +434,13 @@ static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 
static SUNXI_CCU_GATE(usb_ohci3_clk,	"usb-ohci3",	"osc24M",

		      0x0cc, BIT(19), 0);



static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };

static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,

/* H3 has broken MDFS hardware, so the mux/divider cannot be changed. */

static CLK_FIXED_FACTOR_HW(h3_dram_clk, "dram",

			   &pll_ddr_clk.common.hw,

			   1, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);



static const char * const h5_dram_parents[] = { "pll-ddr", "pll-periph0-2x" };

static SUNXI_CCU_M_WITH_MUX(h5_dram_clk, "dram", h5_dram_parents,

			    0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);



static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
@@ -592,7 +597,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = { 
	&usb_ohci1_clk.common,

	&usb_ohci2_clk.common,

	&usb_ohci3_clk.common,

	&dram_clk.common,

	&h5_dram_clk.common,

	&dram_ve_clk.common,

	&dram_csi_clk.common,

	&dram_deinterlace_clk.common,
@@ -732,7 +737,7 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = { 
		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,

		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,

		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,

		[CLK_DRAM]		= &dram_clk.common.hw,

		[CLK_DRAM]		= &h3_dram_clk.hw,

		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,

		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,

		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
@@ -848,7 +853,7 @@ static struct clk_hw_onecell_data sun50i_h5_hw_clks = { 
		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,

		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,

		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,

		[CLK_DRAM]		= &dram_clk.common.hw,

		[CLK_DRAM]		= &h5_dram_clk.common.hw,

		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,

		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,

		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,

drivers/clk/sunxi-ng/ccu_mmc_timing.c

+4 −4
Original line number Diff line number Diff line
@@ -10,11 +10,11 @@ 
#include "ccu_common.h"



/**

 * sunxi_ccu_set_mmc_timing_mode: Configure the MMC clock timing mode

 * sunxi_ccu_set_mmc_timing_mode - Configure the MMC clock timing mode

 * @clk: clock to be configured

 * @new_mode: true for new timing mode introduced in A83T and later

 *

 * Returns 0 on success, -ENOTSUPP if the clock does not support

 * Return: %0 on success, %-ENOTSUPP if the clock does not support

 * switching modes.

 */

int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
@@ -46,8 +46,8 @@ EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode); 
 * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode

 * @clk: clock to query

 *

 * Returns 0 if the clock is in old timing mode, > 0 if it is in

 * new timing mode, and -ENOTSUPP if the clock does not support

 * Return: %0 if the clock is in old timing mode, > %0 if it is in

 * new timing mode, and %-ENOTSUPP if the clock does not support

 * this function.

 */

int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)