Commit 792d6827 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and... 

Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and 'clk-amlogic' into clk-next

 - Support for Versa 5P49V60 clks

* clk-cleanup:
  clk: rs9: Drop unused pin_xin field
  clk: sprd: Add dependency for SPRD_UMS512_CLK
  clk: ralink: fix 'mt7621_gate_is_enabled()' function
  dt-bindings: clock: remove stih416 bindings
  drivers/clk: Remove "select SRCU"

* clk-bindings:
  dt-bindings: clock: qcom,sm8450-camcc: constrain required-opps
  dt-bindings: clock: imx8m-clock: correct i.MX8MQ node name

* clk-renesas:
  clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
  clk: renesas: r8a779g0: Add CAN-FD clocks
  clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC
  clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC
  clk: renesas: r8a779g0: Add custom clock for PLL2
  clk: renesas: cpg-mssr: Remove superfluous check in resume code
  clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence
  clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed
  clk: renesas: r9a07g044: Add clock and reset entries for CRU
  clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
  clk: renesas: r9a09g011: Add USB clock and reset entries
  clk: renesas: r9a09g011: Add TIM clock and reset entries
  clk: renesas: r8a779g0: Add display related clocks
  clk: renesas: rcar-gen4: Restore PLL enum sort order
  clk: renesas: r8a779g0: Fix OSC predividers
  clk: renesas: r9a09g011: Add PWM clock and reset entries

* clk-versa:
  dt-bindings: clock: versaclock5: Document 5P49V60 compatible string
  clk: vc5: Add support for 5P49V60
  clk: vc5: Use `clamp()` to restrict PLL range

* clk-amlogic:
  clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
  clk: meson: sclk-div: switch from .round_rate to .determine_rate
  clk: meson: dualdiv: switch from .round_rate to .determine_rate
  clk: meson: mpll: Switch from .round_rate to .determine_rate
parents d065155e 2c3aa5b1 3ef6d9b3 def70790 df43ce48

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ properties: 
      - idt,5p49v5925

      - idt,5p49v5933

      - idt,5p49v5935

      - idt,5p49v60

      - idt,5p49v6901

      - idt,5p49v6965

      - idt,5p49v6975

Documentation/devicetree/bindings/clock/imx8m-clock.yaml

+1 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ examples: 
    };



  - |

    clock-controller@30390000 {

    clock-controller@30380000 {

        compatible = "fsl,imx8mq-ccm";

        reg = <0x30380000 0x10000>;

        #clock-cells = <1>;

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ properties: 
      A phandle and PM domain specifier for the MMCX power domain.



  required-opps:

    maxItems: 1

    description:

      A phandle to an OPP node describing required MMCX performance point.

drivers/clk/clk-versaclock5.c

+22 −6
Original line number Diff line number Diff line
@@ -122,9 +122,8 @@ 
#define VC5_GLOBAL_REGISTER			0x76

#define VC5_GLOBAL_REGISTER_GLOBAL_RESET	BIT(5)



/* PLL/VCO runs between 2.5 GHz and 3.0 GHz */

/* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */

#define VC5_PLL_VCO_MIN				2500000000UL

#define VC5_PLL_VCO_MAX				3000000000UL



/* VC5 Input mux settings */

#define VC5_MUX_IN_XIN		BIT(0)
@@ -150,6 +149,7 @@ enum vc5_model { 
	IDT_VC5_5P49V5925,

	IDT_VC5_5P49V5933,

	IDT_VC5_5P49V5935,

	IDT_VC6_5P49V60,

	IDT_VC6_5P49V6901,

	IDT_VC6_5P49V6965,

	IDT_VC6_5P49V6975,
@@ -161,6 +161,7 @@ struct vc5_chip_info { 
	const unsigned int	clk_fod_cnt;

	const unsigned int	clk_out_cnt;

	const u32		flags;

	const unsigned long	vco_max;

};



struct vc5_driver_data;
@@ -446,13 +447,11 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
			       unsigned long *parent_rate)

{

	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);

	struct vc5_driver_data *vc5 = hwdata->vc5;

	u32 div_int;

	u64 div_frc;



	if (rate < VC5_PLL_VCO_MIN)

		rate = VC5_PLL_VCO_MIN;

	if (rate > VC5_PLL_VCO_MAX)

		rate = VC5_PLL_VCO_MAX;

	rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);



	/* Determine integer part, which is 12 bit wide */

	div_int = rate / *parent_rate;
@@ -1212,6 +1211,7 @@ static const struct vc5_chip_info idt_5p49v5923_info = { 
	.clk_fod_cnt = 2,

	.clk_out_cnt = 3,

	.flags = 0,

	.vco_max = 3000000000UL,

};



static const struct vc5_chip_info idt_5p49v5925_info = {
@@ -1219,6 +1219,7 @@ static const struct vc5_chip_info idt_5p49v5925_info = { 
	.clk_fod_cnt = 4,

	.clk_out_cnt = 5,

	.flags = 0,

	.vco_max = 3000000000UL,

};



static const struct vc5_chip_info idt_5p49v5933_info = {
@@ -1226,6 +1227,7 @@ static const struct vc5_chip_info idt_5p49v5933_info = { 
	.clk_fod_cnt = 2,

	.clk_out_cnt = 3,

	.flags = VC5_HAS_INTERNAL_XTAL,

	.vco_max = 3000000000UL,

};



static const struct vc5_chip_info idt_5p49v5935_info = {
@@ -1233,6 +1235,15 @@ static const struct vc5_chip_info idt_5p49v5935_info = { 
	.clk_fod_cnt = 4,

	.clk_out_cnt = 5,

	.flags = VC5_HAS_INTERNAL_XTAL,

	.vco_max = 3000000000UL,

};



static const struct vc5_chip_info idt_5p49v60_info = {

	.model = IDT_VC6_5P49V60,

	.clk_fod_cnt = 4,

	.clk_out_cnt = 5,

	.flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,

	.vco_max = 2700000000UL,

};



static const struct vc5_chip_info idt_5p49v6901_info = {
@@ -1240,6 +1251,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = { 
	.clk_fod_cnt = 4,

	.clk_out_cnt = 5,

	.flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,

	.vco_max = 3000000000UL,

};



static const struct vc5_chip_info idt_5p49v6965_info = {
@@ -1247,6 +1259,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = { 
	.clk_fod_cnt = 4,

	.clk_out_cnt = 5,

	.flags = VC5_HAS_BYPASS_SYNC_BIT,

	.vco_max = 3000000000UL,

};



static const struct vc5_chip_info idt_5p49v6975_info = {
@@ -1254,6 +1267,7 @@ static const struct vc5_chip_info idt_5p49v6975_info = { 
	.clk_fod_cnt = 4,

	.clk_out_cnt = 5,

	.flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,

	.vco_max = 3000000000UL,

};



static const struct i2c_device_id vc5_id[] = {
@@ -1261,6 +1275,7 @@ static const struct i2c_device_id vc5_id[] = { 
	{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },

	{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },

	{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },

	{ "5p49v60", .driver_data = IDT_VC6_5P49V60 },

	{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },

	{ "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },

	{ "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
@@ -1273,6 +1288,7 @@ static const struct of_device_id clk_vc5_of_match[] = { 
	{ .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },

	{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },

	{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },

	{ .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },

	{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },

	{ .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },

	{ .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },

drivers/clk/meson/clk-cpu-dyndiv.c

+4 −5
Original line number Diff line number Diff line
@@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, 
				   NULL, 0, data->div.width);

}



static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,

					    unsigned long rate,

					    unsigned long *prate)

static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw,

					       struct clk_rate_request *req)

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);



	return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);

	return divider_determine_rate(hw, req, NULL, data->div.width, 0);

}



static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, 


const struct clk_ops meson_clk_cpu_dyndiv_ops = {

	.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,

	.round_rate = meson_clk_cpu_dyndiv_round_rate,

	.determine_rate = meson_clk_cpu_dyndiv_determine_rate,

	.set_rate = meson_clk_cpu_dyndiv_set_rate,

};

EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);