intel_idle: add core C6 optimization for SPR

mainline inclusion
from mainline-v5.18-rc1
commit 3a9cf77b
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECY


CVE: NA

Intel-SIG: commit 3a9cf77b intel_idle: add core C6 optimization for SPR.
Backport intel_idle driver

--------------------------------

Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake
Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to
match core C6 values, instead of using the default package C6 values.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: yingbao jia <yingbao.jia@intel.com>
Signed-off-by: Jun Tian <jun.j.tian@intel.com>