Commit 3a9cf77b authored by Artem Bityutskiy's avatar Artem Bityutskiy Committed by Rafael J. Wysocki
Browse files

intel_idle: add core C6 optimization for SPR 



Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake
Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to
match core C6 values, instead of using the default package C6 values.

Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent da0e58c0

drivers/idle/intel_idle.c

+15 −0
Original line number Diff line number Diff line
@@ -1578,6 +1578,8 @@ static void __init skx_idle_state_table_update(void) 
 */

static void __init spr_idle_state_table_update(void)

{

	unsigned long long msr;



	/* Check if user prefers C1E over C1. */

	if (preferred_states_mask & BIT(2)) {

		if (preferred_states_mask & BIT(1))
@@ -1591,6 +1593,19 @@ static void __init spr_idle_state_table_update(void) 
		c1e_promotion_enable();

		disable_promotion_to_c1e = false;

	}



	/*

	 * By default, the C6 state assumes the worst-case scenario of package

	 * C6. However, if PC6 is disabled, we update the numbers to match

	 * core C6.

	 */

	rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);



	/* Limit value 2 and above allow for PC6. */

	if ((msr & 0x7) < 2) {

		spr_cstates[2].exit_latency = 190;

		spr_cstates[2].target_residency = 600;

	}

}



static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)