Commit 5e4cb0af authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'mediatek-drm-next-5.20' of... 

Merge tag 'mediatek-drm-next-5.20' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux

 into drm-next

Mediatek DRM Next for Linux 5.20

1. Add Mediatek Soc DRM (vdosys0) support for mt8195
2. Cooperate with DSI RX devices to modify dsi funcs and delay mipi high to cooperate with panel sequence
3. Add mt8186 dsi compatible and convert dsi_dtbinding to .yaml
4. Add MediaTek SoC DRM (vdosys1) support for mt8195
5. Add MT8195 dp_intf driver

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

[airlied: fix drm_edid.h include]
From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220709142021.24260-1-chunkuang.hu@kernel.org
parents 8daecf61 d86c1568

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

+6 −5
Original line number Diff line number Diff line
@@ -4,16 +4,16 @@ 
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: mediatek DPI Controller Device Tree Bindings

title: MediaTek DPI and DP_INTF Controller



maintainers:

  - CK Hu <ck.hu@mediatek.com>

  - Jitao shi <jitao.shi@mediatek.com>



description: |

  The Mediatek DPI function block is a sink of the display subsystem and

  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel

  output bus.

  The MediaTek DPI and DP_INTF function blocks are a sink of the display

  subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a

  parallel output bus.



properties:

  compatible:
@@ -24,6 +24,7 @@ properties: 
      - mediatek,mt8183-dpi

      - mediatek,mt8186-dpi

      - mediatek,mt8192-dpi

      - mediatek,mt8195-dp-intf



  reg:

    maxItems: 1
@@ -55,7 +56,7 @@ properties: 
    $ref: /schemas/graph.yaml#/properties/port

    description:

      Output port node. This port should be connected to the input port of an

      attached HDMI or LVDS encoder chip.

      attached HDMI, LVDS or DisplayPort encoder chip.



required:

  - compatible

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt

deleted100644 → 0
+0 −62
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Mediatek DSI Device

===================



The Mediatek DSI function block is a sink of the display subsystem and can

drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-

channel output.



Required properties:

- compatible: "mediatek,<chip>-dsi"

- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.

- reg: Physical base address and length of the controller's registers

- interrupts: The interrupt signal from the function block.

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- clock-names: must contain "engine", "digital", and "hs"

- phys: phandle link to the MIPI D-PHY controller.

- phy-names: must contain "dphy"

- port: Output port node with endpoint definitions as described in

  Documentation/devicetree/bindings/graph.txt. This port should be connected

  to the input port of an attached DSI panel or DSI-to-eDP encoder chip.



Optional properties:

- resets: list of phandle + reset specifier pair, as described in [1].



[1] Documentation/devicetree/bindings/reset/reset.txt



MIPI TX Configuration Module

============================



See phy/mediatek,dsi-phy.yaml



Example:



mipi_tx0: mipi-dphy@10215000 {

	compatible = "mediatek,mt8173-mipi-tx";

	reg = <0 0x10215000 0 0x1000>;

	clocks = <&clk26m>;

	clock-output-names = "mipi_tx0_pll";

	#clock-cells = <0>;

	#phy-cells = <0>;

	drive-strength-microamp = <4600>;

	nvmem-cells= <&mipi_tx_calibration>;

	nvmem-cell-names = "calibration-data";

};



dsi0: dsi@1401b000 {

	compatible = "mediatek,mt8173-dsi";

	reg = <0 0x1401b000 0 0x1000>;

	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,

		 <&mipi_tx0>;

	clock-names = "engine", "digital", "hs";

	resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;

	phys = <&mipi_tx0>;

	phy-names = "dphy";



	port {

		dsi0_out: endpoint {

			remote-endpoint = <&panel_in>;

		};

	};

};

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek DSI Controller Device Tree Bindings



maintainers:

  - Chun-Kuang Hu <chunkuang.hu@kernel.org>

  - Philipp Zabel <p.zabel@pengutronix.de>

  - Jitao Shi <jitao.shi@mediatek.com>

  - Xinlei Lee <xinlei.lee@mediatek.com>



description: |

  The MediaTek DSI function block is a sink of the display subsystem and can

  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-

  channel output.



allOf:

  - $ref: /schemas/display/dsi-controller.yaml#



properties:

  compatible:

    enum:

      - mediatek,mt2701-dsi

      - mediatek,mt7623-dsi

      - mediatek,mt8167-dsi

      - mediatek,mt8173-dsi

      - mediatek,mt8183-dsi

      - mediatek,mt8186-dsi



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: Engine Clock

      - description: Digital Clock

      - description: HS Clock



  clock-names:

    items:

      - const: engine

      - const: digital

      - const: hs



  resets:

    maxItems: 1



  phys:

    maxItems: 1



  phy-names:

    items:

      - const: dphy



  port:

    $ref: /schemas/graph.yaml#/properties/port

    description:

      Output port node. This port should be connected to the input

      port of an attached DSI panel or DSI-to-eDP encoder chip.



required:

  - compatible

  - reg

  - interrupts

  - power-domains

  - clocks

  - clock-names

  - phys

  - phy-names

  - port



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8183-clk.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/power/mt8183-power.h>

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/reset/mt8183-resets.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        dsi0: dsi@14014000 {

            compatible = "mediatek,mt8183-dsi";

            reg = <0 0x14014000 0 0x1000>;

            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;

            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

            clocks = <&mmsys CLK_MM_DSI0_MM>,

                <&mmsys CLK_MM_DSI0_IF>,

                <&mipi_tx0>;

            clock-names = "engine", "digital", "hs";

            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;

            phys = <&mipi_tx0>;

            phy-names = "dphy";

            port {

                dsi0_out: endpoint {

                    remote-endpoint = <&panel_in>;

                };

            };

        };

    };



...

Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml

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+88 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek MDP RDMA



maintainers:

  - Chun-Kuang Hu <chunkuang.hu@kernel.org>

  - Philipp Zabel <p.zabel@pengutronix.de>



description:

  The MediaTek MDP RDMA stands for Read Direct Memory Access.

  It provides real time data to the back-end panel driver, such as DSI,

  DPI and DP_INTF.

  It contains one line buffer to store the sufficient pixel data.

  RDMA device node must be siblings to the central MMSYS_CONFIG node.

  For a description of the MMSYS_CONFIG binding, see

  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.



properties:

  compatible:

    const: mediatek,mt8195-vdo1-rdma



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: RDMA Clock



  iommus:

    maxItems: 1



  mediatek,gce-client-reg:

    description:

      The register of display function block to be set by gce. There are 4 arguments,

      such as gce node, subsys id, offset and register size. The subsys id that is

      mapping to the register of display function blocks is defined in the gce header

      include/dt-bindings/gce/<chip>-gce.h of each chips.

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      items:

        - description: phandle of GCE

        - description: GCE subsys id

        - description: register offset

        - description: register size

    maxItems: 1



required:

  - compatible

  - reg

  - power-domains

  - clocks

  - iommus

  - mediatek,gce-client-reg



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/mt8195-clk.h>

    #include <dt-bindings/power/mt8195-power.h>

    #include <dt-bindings/gce/mt8195-gce.h>

    #include <dt-bindings/memory/mt8195-memory-port.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        rdma@1c104000 {

            compatible = "mediatek,mt8195-vdo1-rdma";

            reg = <0 0x1c104000 0 0x1000>;

            interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;

            clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;

            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

            iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;

            mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;

        };

    };

drivers/gpu/drm/mediatek/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \ 
		  mtk_disp_ccorr.o \

		  mtk_disp_color.o \

		  mtk_disp_gamma.o \

		  mtk_disp_merge.o \

		  mtk_disp_ovl.o \

		  mtk_disp_rdma.o \

		  mtk_drm_crtc.o \
@@ -12,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \ 
		  mtk_drm_gem.o \

		  mtk_drm_plane.o \

		  mtk_dsi.o \

		  mtk_dpi.o

		  mtk_dpi.o \

		  mtk_mdp_rdma.o



obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o