Commit 54c9c9bb authored by Fenghua Yu's avatar Fenghua Yu Committed by Xiaochen Shen
Browse files

Documentation/x86: Document resctrl's new sparse_masks

mainline inclusion
from mainline-v6.7-rc1
commit aaa5fa35743ab9f0726568611a85e3e15349b9bf
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8WO9B
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aaa5fa35743ab9f0726568611a85e3e15349b9bf



--------------------------------

The documentation mentions that non-contiguous bit masks are not
supported in Intel Cache Allocation Technology (CAT).

Update the documentation on how to determine if sparse bit masks are
allowed in L2 and L3 CAT.

Intel-SIG: commit aaa5fa35743a Documentation/x86: Document resctrl's new sparse_masks.
Incremental backporting patches for Intel RDT on Intel Xeon platform.

Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Signed-off-by: default avatarMaciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: default avatarPeter Newman <peternewman@google.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Tested-by: default avatarPeter Newman <peternewman@google.com>
Link: https://lore.kernel.org/r/3e9610997164f648e15c5c2e90d4944ce36504fe.1696934091.git.maciej.wieczor-retman@intel.com


Signed-off-by: default avatarXiaochen Shen <xiaochen.shen@intel.com>
parent ad226e52
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