Commit 54c9c9bb authored by Fenghua Yu's avatar Fenghua Yu Committed by Xiaochen Shen
Browse files

Documentation/x86: Document resctrl's new sparse_masks 

mainline inclusion
from mainline-v6.7-rc1
commit aaa5fa35743ab9f0726568611a85e3e15349b9bf
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8WO9B
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aaa5fa35743ab9f0726568611a85e3e15349b9bf



--------------------------------

The documentation mentions that non-contiguous bit masks are not
supported in Intel Cache Allocation Technology (CAT).

Update the documentation on how to determine if sparse bit masks are
allowed in L2 and L3 CAT.

Intel-SIG: commit aaa5fa35743a Documentation/x86: Document resctrl's new sparse_masks.
Incremental backporting patches for Intel RDT on Intel Xeon platform.

Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Signed-off-by: default avatarMaciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: default avatarPeter Newman <peternewman@google.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Tested-by: default avatarPeter Newman <peternewman@google.com>
Link: https://lore.kernel.org/r/3e9610997164f648e15c5c2e90d4944ce36504fe.1696934091.git.maciej.wieczor-retman@intel.com


Signed-off-by: default avatarXiaochen Shen <xiaochen.shen@intel.com>
parent ad226e52

Documentation/arch/x86/resctrl.rst

+12 −4
Original line number Diff line number Diff line
@@ -124,6 +124,13 @@ related to allocation: 
			"P":

			      Corresponding region is pseudo-locked. No

			      sharing allowed.

"sparse_masks":

		Indicates if non-contiguous 1s value in CBM is supported.



			"0":

			      Only contiguous 1s value in CBM is supported.

			"1":

			      Non-contiguous 1s value in CBM is supported.



Memory bandwidth(MB) subdirectory contains the following files

with respect to allocation:
@@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available 
for allocation using a bitmask. The maximum value of the mask is defined

by each cpu model (and may be different for different cache levels). It

is found using CPUID, but is also provided in the "info" directory of

the resctrl file system in "info/{resource}/cbm_mask". Intel hardware

the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware

requires that these masks have all the '1' bits in a contiguous block. So

0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9

and 0xA are not.  On a system with a 20-bit mask each bit represents 5%

of the capacity of the cache. You could partition the cache into four

equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.

and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks

if non-contiguous 1s value is supported. On a system with a 20-bit mask

each bit represents 5% of the capacity of the cache. You could partition

the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.



Memory bandwidth Allocation and monitoring

==========================================