perf/x86: Hybrid PMU support for hardware cache event

mainline inclusion
from mainline-v5.13-rc1
commit 0d18f2df
category: feature
feature: SRF core PMU support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RWG5
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d18f2dfead8dd63bf1186c9ef38528d6a615a55



Intel-SIG: commit 0d18f2df perf/x86: Hybrid PMU support for hardware cache event
Backport as a dependency for Sierra Forrest core PMU support.

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The hardware cache events are different among hybrid PMUs. Each hybrid
PMU should have its own hw cache event table.

Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1618237865-33448-9-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>