Commit 53ab78cd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "A couple driver fixes in the clk subsystem

   - Fix a hang due to bad clk parent in the Ingenic jz4725b driver

   - Fix SD controllers on Qualcomm MSM8994 SoCs by removing clks that
     shouldn't be touched"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: jz4725b: fix mmc0 clock gating
  clk: qcom: gcc-msm8994: Remove NoC clocks
parents 5ee3d001 2f0754f2

drivers/clk/ingenic/jz4725b-cgu.c

+1 −2
Original line number Diff line number Diff line
@@ -139,11 +139,10 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { 
	},



	[JZ4725B_CLK_I2S] = {

		"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,

		"i2s", CGU_CLK_MUX | CGU_CLK_DIV,

		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },

		.mux = { CGU_REG_CPCCR, 31, 1 },

		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },

		.gate = { CGU_REG_CLKGR, 6 },

	},



	[JZ4725B_CLK_SPI] = {

drivers/clk/qcom/gcc-msm8994.c

+9 −97
Original line number Diff line number Diff line
@@ -108,42 +108,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 
	{ .hw = &gpll4.clkr.hw },

};



static struct clk_rcg2 system_noc_clk_src = {

	.cmd_rcgr = 0x0120,

	.hid_width = 5,

	.parent_map = gcc_xo_gpll0_map,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "system_noc_clk_src",

		.parent_data = gcc_xo_gpll0,

		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),

		.ops = &clk_rcg2_ops,

	},

};



static struct clk_rcg2 config_noc_clk_src = {

	.cmd_rcgr = 0x0150,

	.hid_width = 5,

	.parent_map = gcc_xo_gpll0_map,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "config_noc_clk_src",

		.parent_data = gcc_xo_gpll0,

		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),

		.ops = &clk_rcg2_ops,

	},

};



static struct clk_rcg2 periph_noc_clk_src = {

	.cmd_rcgr = 0x0190,

	.hid_width = 5,

	.parent_map = gcc_xo_gpll0_map,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "periph_noc_clk_src",

		.parent_data = gcc_xo_gpll0,

		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),

		.ops = &clk_rcg2_ops,

	},

};



static struct freq_tbl ftbl_ufs_axi_clk_src[] = {

	F(50000000, P_GPLL0, 12, 0, 0),

	F(100000000, P_GPLL0, 6, 0, 0),
@@ -1150,8 +1114,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = { 
		.enable_mask = BIT(17),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_blsp1_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1435,8 +1397,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = { 
		.enable_mask = BIT(15),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_blsp2_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1764,8 +1724,6 @@ static struct clk_branch gcc_lpass_q6_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_lpass_q6_axi_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1778,8 +1736,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mss_q6_bimc_axi_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1807,9 +1763,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1822,9 +1775,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_mstr_axi_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1854,9 +1804,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_slv_axi_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1884,9 +1831,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1899,9 +1843,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_mstr_axi_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1930,9 +1871,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_slv_axi_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1960,8 +1898,6 @@ static struct clk_branch gcc_pdm_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pdm_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1989,9 +1925,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc1_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2004,9 +1937,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc2_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2034,9 +1964,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc3_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2064,9 +1991,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc4_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2124,8 +2048,6 @@ static struct clk_branch gcc_tsif_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_tsif_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2153,8 +2075,6 @@ static struct clk_branch gcc_ufs_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2198,8 +2118,6 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_rx_symbol_0_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2213,8 +2131,6 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_rx_symbol_1_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2243,8 +2159,6 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_tx_symbol_0_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2258,8 +2172,6 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_tx_symbol_1_clk",

			.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2364,8 +2276,6 @@ static struct clk_branch gcc_usb_hs_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_usb_hs_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2488,8 +2398,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { 
		.enable_mask = BIT(10),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_boot_rom_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2503,8 +2411,6 @@ static struct clk_branch gcc_prng_ahb_clk = { 
		.enable_mask = BIT(13),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_prng_ahb_clk",

			.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2547,9 +2453,6 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { 
	[GPLL0] = &gpll0.clkr,

	[GPLL4_EARLY] = &gpll4_early.clkr,

	[GPLL4] = &gpll4.clkr,

	[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,

	[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,

	[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,

	[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,

	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,

	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -2696,6 +2599,15 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { 
	[USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,

	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,

	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,



	/*

	 * The following clocks should NOT be managed by this driver, but they once were

	 * mistakengly added. Now they are only here to indicate that they are not defined

	 * on purpose, even though the names will stay in the header file (for ABI sanity).

	 */

	[CONFIG_NOC_CLK_SRC] = NULL,

	[PERIPH_NOC_CLK_SRC] = NULL,

	[SYSTEM_NOC_CLK_SRC] = NULL,

};



static struct gdsc *gcc_msm8994_gdscs[] = {