Commit 5ee3d001 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-02-25' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Regular drm fixes pull, i915, amdgpu and tegra mostly, all pretty
  small.

  core:
   - edid: Always set RGB444

  tegra:
   - tegra186 suspend/resume fixes
   - syncpoint wait fix
   - build warning fix
   - eDP on older devices fix

  amdgpu:
   - Display FP fix
   - PCO powergating fix
   - RDNA2 OEM SKU stability fixes
   - Display PSR fix
   - PCI ASPM fix
   - Display link encoder fix for TEST_COMMIT
   - Raven2 suspend/resume fix
   - Fix a regression in virtual display support
   - GPUVM eviction fix

  i915:
   - Fix QGV handling on ADL-P+
   - Fix bw atomic check when switching between SAGV vs. no SAGV
   - Disconnect PHYs left connected by BIOS on disabled ports
   - Fix SAVG to no SAGV transitions on TGL+
   - Print PHY name properly on calibration error (DG2)

  imx:
   - dcss: Select GEM CMA helpers

  radeon:
   - Fix some variables's type

  vc4:
   - Fix codec cleanup
   - Fix PM reference counting"

* tag 'drm-fixes-2022-02-25' of git://anongit.freedesktop.org/drm/drm: (24 commits)
  drm/amdgpu: check vm ready by amdgpu_vm->evicting flag
  drm/amdgpu: bypass tiling flag check in virtual display case (v2)
  Revert "drm/amdgpu: add modifiers in amdgpu_vkms_plane_init()"
  drm/amdgpu: do not enable asic reset for raven2
  drm/amd/display: Fix stream->link_enc unassigned during stream removal
  drm/amd: Check if ASPM is enabled from PCIe subsystem
  drm/edid: Always set RGB444
  drm/tegra: dpaux: Populate AUX bus
  drm/radeon: fix variable type
  drm/amd/display: For vblank_disable_immediate, check PSR is really used
  drm/amd/pm: fix some OEM SKU specific stability issues
  drm/amdgpu: disable MMHUB PG for Picasso
  drm/amd/display: Protect update_bw_bounding_box FPU code.
  drm/i915/dg2: Print PHY name properly on calibration error
  drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV
  drm/i915: Correctly populate use_sagv_wm for all pipes
  drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
  drm/i915: Widen the QGV point mask
  drm/imx/dcss: i.MX8MQ DCSS select DRM_GEM_CMA_HELPER
  drm/vc4: crtc: Fix runtime_pm reference counting
  ...
parents 7ee02256 ecf8a99f
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+1 −1
Original line number Diff line number Diff line
@@ -1141,7 +1141,7 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev,
	if (ret)
		return ret;

	if (!dev->mode_config.allow_fb_modifiers) {
	if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) {
		drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
			      "GFX9+ requires FB check based on format modifier\n");
		ret = check_tiling_flags_gfx6(rfb);
+3 −0
Original line number Diff line number Diff line
@@ -2011,6 +2011,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
			return -ENODEV;
	}

	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
		amdgpu_aspm = 0;

	if (amdgpu_virtual_display ||
	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
		supports_atomic = true;
+1 −2
Original line number Diff line number Diff line
@@ -391,7 +391,6 @@ static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
						int index)
{
	struct drm_plane *plane;
	uint64_t modifiers[] = {DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID};
	int ret;

	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
@@ -402,7 +401,7 @@ static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
				       &amdgpu_vkms_plane_funcs,
				       amdgpu_vkms_formats,
				       ARRAY_SIZE(amdgpu_vkms_formats),
				       modifiers, type, NULL);
				       NULL, type, NULL);
	if (ret) {
		kfree(plane);
		return ERR_PTR(ret);
+7 −2
Original line number Diff line number Diff line
@@ -768,11 +768,16 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 * Check if all VM PDs/PTs are ready for updates
 *
 * Returns:
 * True if eviction list is empty.
 * True if VM is not evicting.
 */
bool amdgpu_vm_ready(struct amdgpu_vm *vm)
{
	return list_empty(&vm->evicted);
	bool ret;

	amdgpu_vm_eviction_lock(vm);
	ret = !vm->evicting;
	amdgpu_vm_eviction_unlock(vm);
	return ret;
}

/**
+6 −3
Original line number Diff line number Diff line
@@ -619,8 +619,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
static int soc15_asic_reset(struct amdgpu_device *adev)
{
	/* original raven doesn't have full asic reset */
	if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
	    !(adev->apu_flags & AMD_APU_IS_RAVEN2))
	if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
	    (adev->apu_flags & AMD_APU_IS_RAVEN2))
		return 0;

	switch (soc15_asic_reset_method(adev)) {
@@ -1114,8 +1114,11 @@ static int soc15_common_early_init(void *handle)
				AMD_CG_SUPPORT_SDMA_LS |
				AMD_CG_SUPPORT_VCN_MGCG;

			/*
			 * MMHUB PG needs to be disabled for Picasso for
			 * stability reasons.
			 */
			adev->pg_flags = AMD_PG_SUPPORT_SDMA |
				AMD_PG_SUPPORT_MMHUB |
				AMD_PG_SUPPORT_VCN;
		} else {
			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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