Commit 2f0754f2 authored by Siarhei Volkau's avatar Siarhei Volkau Committed by Stephen Boyd
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clk: jz4725b: fix mmc0 clock gating 



The mmc0 clock gate bit was mistakenly assigned to "i2s" clock.
You can find that the same bit is assigned to "mmc0" too.
It leads to mmc0 hang for a long time after any sound activity
also it  prevented PM_SLEEP to work properly.
I guess it was introduced by copy-paste from jz4740 driver
where it is really controls I2S clock gate.

Fixes: 226dfa47 ("clk: Add Ingenic jz4725b CGU driver")
Signed-off-by: default avatarSiarhei Volkau <lis8215@gmail.com>
Tested-by: default avatarSiarhei Volkau <lis8215@gmail.com>
Reviewed-by: default avatarPaul Cercueil <paul@crapouillou.net>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220205171849.687805-2-lis8215@gmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 3494894a

drivers/clk/ingenic/jz4725b-cgu.c

+1 −2
Original line number Diff line number Diff line
@@ -139,11 +139,10 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { 
	},



	[JZ4725B_CLK_I2S] = {

		"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,

		"i2s", CGU_CLK_MUX | CGU_CLK_DIV,

		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },

		.mux = { CGU_REG_CPCCR, 31, 1 },

		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },

		.gate = { CGU_REG_CLKGR, 6 },

	},



	[JZ4725B_CLK_SPI] = {