Commit 3462100c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next 

 - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
 - Remove non-OF mmp clk drivers
 - Move number of clks from DT headers to drivers

* clk-imx:
  clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
  clk: imx: pll14xx: align pdiv with reference manual
  clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
  clk: imx25: make __mx25_clocks_init return void
  clk: imx25: print silicon revision during init
  dt-bindings: clocks: imx8mp: make sai4 a dummy clock
  clk: imx8mp: fix sai4 clock
  clk: imx: imx8ulp: update SPLL2 type
  clk: imx: pllv4: Fix SPLL2 MULT range
  clk: imx: imx8: add audio clock mux driver
  dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
  clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
  clk: imx: clk-gpr-mux: Simplify .determine_rate()
  clk: imx: Add 519.75MHz frequency support for imx9 pll
  clk: imx93: Add PDM IPG clk
  dt-bindings: clock: imx93: Add PDM IPG clk

* clk-samsung:
  dt-bindings: clock: samsung: remove define with number of clocks
  clk: samsung: exynoautov9: do not define number of clocks in bindings
  clk: samsung: exynos850: do not define number of clocks in bindings
  clk: samsung: exynos7885: do not define number of clocks in bindings
  clk: samsung: exynos5433: do not define number of clocks in bindings
  clk: samsung: exynos5420: do not define number of clocks in bindings
  clk: samsung: exynos5410: do not define number of clocks in bindings
  clk: samsung: exynos5260: do not define number of clocks in bindings
  clk: samsung: exynos5250: do not define number of clocks in bindings
  clk: samsung: exynos4: do not define number of clocks in bindings
  clk: samsung: exynos3250: do not define number of clocks in bindings

* clk-annotate:
  clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
  clk: Annotate struct clk_hw_onecell_data with __counted_by

* clk-marvell:
  clk: pxa910: Move number of clocks to driver source
  clk: pxa1928: Move number of clocks to driver source
  clk: pxa168: Move number of clocks to driver source
  clk: mmp2: Move number of clocks to driver source
  clk: mmp: Remove old non-OF clock drivers

* clk-lmk:
  clk: lmk04832: Support using PLL1_LD as SPI readback pin
  clk: lmk04832: Don't disable vco clock on probe fail
  clk: lmk04832: Set missing parent_names for output clocks
parents 032bcf78 960535d5 e5546e91 a5be6db5 3b99cd27 6aa8dc69

Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml

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+282 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8 Audio Clock Mux



maintainers:

  - Shengjiu Wang <shengjiu.wang@nxp.com>



description: |

  NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP

  used to control Audio related clock on the SoC.



properties:

  compatible:

    enum:

      - fsl,imx8dxl-acm

      - fsl,imx8qm-acm

      - fsl,imx8qxp-acm



  reg:

    maxItems: 1



  power-domains:

    minItems: 13

    maxItems: 21



  '#clock-cells':

    const: 1

    description:

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h

      for the full list of i.MX8 ACM clock IDs.



  clocks:

    minItems: 13

    maxItems: 27



  clock-names:

    minItems: 13

    maxItems: 27



required:

  - compatible

  - reg

  - power-domains

  - '#clock-cells'

  - clocks

  - clock-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qxp-acm

    then:

      properties:

        power-domains:

          items:

            - description: power domain of IMX_SC_R_AUDIO_CLK_0

            - description: power domain of IMX_SC_R_AUDIO_CLK_1

            - description: power domain of IMX_SC_R_MCLK_OUT_0

            - description: power domain of IMX_SC_R_MCLK_OUT_1

            - description: power domain of IMX_SC_R_AUDIO_PLL_0

            - description: power domain of IMX_SC_R_AUDIO_PLL_1

            - description: power domain of IMX_SC_R_ASRC_0

            - description: power domain of IMX_SC_R_ASRC_1

            - description: power domain of IMX_SC_R_ESAI_0

            - description: power domain of IMX_SC_R_SAI_0

            - description: power domain of IMX_SC_R_SAI_1

            - description: power domain of IMX_SC_R_SAI_2

            - description: power domain of IMX_SC_R_SAI_3

            - description: power domain of IMX_SC_R_SAI_4

            - description: power domain of IMX_SC_R_SAI_5

            - description: power domain of IMX_SC_R_SPDIF_0

            - description: power domain of IMX_SC_R_MQS_0



        clocks:

          minItems: 18

          maxItems: 18



        clock-names:

          items:

            - const: aud_rec_clk0_lpcg_clk

            - const: aud_rec_clk1_lpcg_clk

            - const: aud_pll_div_clk0_lpcg_clk

            - const: aud_pll_div_clk1_lpcg_clk

            - const: ext_aud_mclk0

            - const: ext_aud_mclk1

            - const: esai0_rx_clk

            - const: esai0_rx_hf_clk

            - const: esai0_tx_clk

            - const: esai0_tx_hf_clk

            - const: spdif0_rx

            - const: sai0_rx_bclk

            - const: sai0_tx_bclk

            - const: sai1_rx_bclk

            - const: sai1_tx_bclk

            - const: sai2_rx_bclk

            - const: sai3_rx_bclk

            - const: sai4_rx_bclk



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qm-acm

    then:

      properties:

        power-domains:

          items:

            - description: power domain of IMX_SC_R_AUDIO_CLK_0

            - description: power domain of IMX_SC_R_AUDIO_CLK_1

            - description: power domain of IMX_SC_R_MCLK_OUT_0

            - description: power domain of IMX_SC_R_MCLK_OUT_1

            - description: power domain of IMX_SC_R_AUDIO_PLL_0

            - description: power domain of IMX_SC_R_AUDIO_PLL_1

            - description: power domain of IMX_SC_R_ASRC_0

            - description: power domain of IMX_SC_R_ASRC_1

            - description: power domain of IMX_SC_R_ESAI_0

            - description: power domain of IMX_SC_R_ESAI_1

            - description: power domain of IMX_SC_R_SAI_0

            - description: power domain of IMX_SC_R_SAI_1

            - description: power domain of IMX_SC_R_SAI_2

            - description: power domain of IMX_SC_R_SAI_3

            - description: power domain of IMX_SC_R_SAI_4

            - description: power domain of IMX_SC_R_SAI_5

            - description: power domain of IMX_SC_R_SAI_6

            - description: power domain of IMX_SC_R_SAI_7

            - description: power domain of IMX_SC_R_SPDIF_0

            - description: power domain of IMX_SC_R_SPDIF_1

            - description: power domain of IMX_SC_R_MQS_0



        clocks:

          minItems: 27

          maxItems: 27



        clock-names:

          items:

            - const: aud_rec_clk0_lpcg_clk

            - const: aud_rec_clk1_lpcg_clk

            - const: aud_pll_div_clk0_lpcg_clk

            - const: aud_pll_div_clk1_lpcg_clk

            - const: mlb_clk

            - const: hdmi_rx_mclk

            - const: ext_aud_mclk0

            - const: ext_aud_mclk1

            - const: esai0_rx_clk

            - const: esai0_rx_hf_clk

            - const: esai0_tx_clk

            - const: esai0_tx_hf_clk

            - const: esai1_rx_clk

            - const: esai1_rx_hf_clk

            - const: esai1_tx_clk

            - const: esai1_tx_hf_clk

            - const: spdif0_rx

            - const: spdif1_rx

            - const: sai0_rx_bclk

            - const: sai0_tx_bclk

            - const: sai1_rx_bclk

            - const: sai1_tx_bclk

            - const: sai2_rx_bclk

            - const: sai3_rx_bclk

            - const: sai4_rx_bclk

            - const: sai5_tx_bclk

            - const: sai6_rx_bclk



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8dxl-acm

    then:

      properties:

        power-domains:

          items:

            - description: power domain of IMX_SC_R_AUDIO_CLK_0

            - description: power domain of IMX_SC_R_AUDIO_CLK_1

            - description: power domain of IMX_SC_R_MCLK_OUT_0

            - description: power domain of IMX_SC_R_MCLK_OUT_1

            - description: power domain of IMX_SC_R_AUDIO_PLL_0

            - description: power domain of IMX_SC_R_AUDIO_PLL_1

            - description: power domain of IMX_SC_R_ASRC_0

            - description: power domain of IMX_SC_R_SAI_0

            - description: power domain of IMX_SC_R_SAI_1

            - description: power domain of IMX_SC_R_SAI_2

            - description: power domain of IMX_SC_R_SAI_3

            - description: power domain of IMX_SC_R_SPDIF_0

            - description: power domain of IMX_SC_R_MQS_0



        clocks:

          minItems: 13

          maxItems: 13



        clock-names:

          items:

            - const: aud_rec_clk0_lpcg_clk

            - const: aud_rec_clk1_lpcg_clk

            - const: aud_pll_div_clk0_lpcg_clk

            - const: aud_pll_div_clk1_lpcg_clk

            - const: ext_aud_mclk0

            - const: ext_aud_mclk1

            - const: spdif0_rx

            - const: sai0_rx_bclk

            - const: sai0_tx_bclk

            - const: sai1_rx_bclk

            - const: sai1_tx_bclk

            - const: sai2_rx_bclk

            - const: sai3_rx_bclk



additionalProperties: false



examples:

  # Clock Control Module node:

  - |

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    clock-controller@59e00000 {

        compatible = "fsl,imx8qxp-acm";

        reg = <0x59e00000 0x1d0000>;

        #clock-cells = <1>;

        power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,

                        <&pd IMX_SC_R_AUDIO_CLK_1>,

                        <&pd IMX_SC_R_MCLK_OUT_0>,

                        <&pd IMX_SC_R_MCLK_OUT_1>,

                        <&pd IMX_SC_R_AUDIO_PLL_0>,

                        <&pd IMX_SC_R_AUDIO_PLL_1>,

                        <&pd IMX_SC_R_ASRC_0>,

                        <&pd IMX_SC_R_ASRC_1>,

                        <&pd IMX_SC_R_ESAI_0>,

                        <&pd IMX_SC_R_SAI_0>,

                        <&pd IMX_SC_R_SAI_1>,

                        <&pd IMX_SC_R_SAI_2>,

                        <&pd IMX_SC_R_SAI_3>,

                        <&pd IMX_SC_R_SAI_4>,

                        <&pd IMX_SC_R_SAI_5>,

                        <&pd IMX_SC_R_SPDIF_0>,

                        <&pd IMX_SC_R_MQS_0>;

        clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,

                 <&aud_rec1_lpcg IMX_LPCG_CLK_0>,

                 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,

                 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,

                 <&clk_ext_aud_mclk0>,

                 <&clk_ext_aud_mclk1>,

                 <&clk_esai0_rx_clk>,

                 <&clk_esai0_rx_hf_clk>,

                 <&clk_esai0_tx_clk>,

                 <&clk_esai0_tx_hf_clk>,

                 <&clk_spdif0_rx>,

                 <&clk_sai0_rx_bclk>,

                 <&clk_sai0_tx_bclk>,

                 <&clk_sai1_rx_bclk>,

                 <&clk_sai1_tx_bclk>,

                 <&clk_sai2_rx_bclk>,

                 <&clk_sai3_rx_bclk>,

                 <&clk_sai4_rx_bclk>;

        clock-names = "aud_rec_clk0_lpcg_clk",

                      "aud_rec_clk1_lpcg_clk",

                      "aud_pll_div_clk0_lpcg_clk",

                      "aud_pll_div_clk1_lpcg_clk",

                      "ext_aud_mclk0",

                      "ext_aud_mclk1",

                      "esai0_rx_clk",

                      "esai0_rx_hf_clk",

                      "esai0_tx_clk",

                      "esai0_tx_hf_clk",

                      "spdif0_rx",

                      "sai0_rx_bclk",

                      "sai0_tx_bclk",

                      "sai1_rx_bclk",

                      "sai1_tx_bclk",

                      "sai2_rx_bclk",

                      "sai3_rx_bclk",

                      "sai4_rx_bclk";

    };

drivers/clk/clk-aspeed.c

+1 −2
Original line number Diff line number Diff line
@@ -701,6 +701,7 @@ static void __init aspeed_cc_init(struct device_node *np) 
				  GFP_KERNEL);

	if (!aspeed_clk_data)

		return;

	aspeed_clk_data->num = ASPEED_NUM_CLKS;



	/*

	 * This way all clocks fetched before the platform device probes,
@@ -732,8 +733,6 @@ static void __init aspeed_cc_init(struct device_node *np) 
		aspeed_ast2500_cc(map);

	else

		pr_err("unknown platform, failed to add clocks\n");



	aspeed_clk_data->num = ASPEED_NUM_CLKS;

	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);

	if (ret)

		pr_err("failed to add DT provider: %d\n", ret);

drivers/clk/clk-ast2600.c

+1 −1
Original line number Diff line number Diff line
@@ -839,6 +839,7 @@ static void __init aspeed_g6_cc_init(struct device_node *np) 
				      ASPEED_G6_NUM_CLKS), GFP_KERNEL);

	if (!aspeed_g6_clk_data)

		return;

	aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;



	/*

	 * This way all clocks fetched before the platform device probes,
@@ -860,7 +861,6 @@ static void __init aspeed_g6_cc_init(struct device_node *np) 
	}



	aspeed_g6_cc(map);

	aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;

	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);

	if (ret)

		pr_err("failed to add DT provider: %d\n", ret);

drivers/clk/clk-gemini.c

+1 −1
Original line number Diff line number Diff line
@@ -402,6 +402,7 @@ static void __init gemini_cc_init(struct device_node *np) 
				  GFP_KERNEL);

	if (!gemini_clk_data)

		return;

	gemini_clk_data->num = GEMINI_NUM_CLKS;



	/*

	 * This way all clock fetched before the platform device probes,
@@ -455,7 +456,6 @@ static void __init gemini_cc_init(struct device_node *np) 
	gemini_clk_data->hws[GEMINI_CLK_APB] = hw;



	/* Register the clocks to be accessed by the device tree */

	gemini_clk_data->num = GEMINI_NUM_CLKS;

	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);

}

CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);

drivers/clk/clk-lmk04832.c

+23 −12
Original line number Diff line number Diff line
@@ -134,6 +134,11 @@ 
/* 0x14b - 0x152 Holdover */



/* 0x153 - 0x15f PLL1 Configuration */

#define LMK04832_REG_PLL1_LD		0x15f

#define LMK04832_BIT_PLL1_LD_MUX		GENMASK(7, 3)

#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK		0x07

#define LMK04832_BIT_PLL1_LD_TYPE		GENMASK(2, 0)

#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP		0x03



/* 0x160 - 0x16e PLL2 Configuration */

#define LMK04832_REG_PLL2_R_MSB		0x160
@@ -206,6 +211,7 @@ enum lmk04832_rdbk_type { 
	RDBK_CLKIN_SEL0,

	RDBK_CLKIN_SEL1,

	RDBK_RESET,

	RDBK_PLL1_LD,

};



struct lmk_dclk {
@@ -1297,6 +1303,7 @@ static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num) 
		sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);

		init.name = dclk_name;

		parent_names[0] = clk_hw_get_name(&lmk->vco);

		init.parent_names = parent_names;

		init.ops = &lmk04832_dclk_ops;

		init.flags = CLK_SET_RATE_PARENT;

		init.num_parents = 1;
@@ -1345,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) 
{

	int reg;

	int ret;

	int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,

			     LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |

		  FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,

			     LMK04832_VAL_CLKIN_SEL_TYPE_OUT);



	dev_info(lmk->dev, "setting up 4-wire mode\n");

	ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
@@ -1362,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) 
	case RDBK_RESET:

		reg = LMK04832_REG_CLKIN_RST;

		break;

	case RDBK_PLL1_LD:

		reg = LMK04832_REG_PLL1_LD;

		val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,

				 LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |

		      FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,

				 LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);

		break;

	default:

		return -EINVAL;

	}



	return regmap_write(lmk->regmap, reg,

			    FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,

				       LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |

			    FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,

				       LMK04832_VAL_CLKIN_SEL_TYPE_OUT));

	return regmap_write(lmk->regmap, reg, val);

}



static int lmk04832_probe(struct spi_device *spi)
@@ -1504,21 +1518,21 @@ static int lmk04832_probe(struct spi_device *spi) 
		ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);

		if (ret) {

			dev_err(lmk->dev, "failed to set VCO rate\n");

			goto err_disable_vco;

			goto err_disable_oscin;

		}

	}



	ret = lmk04832_register_sclk(lmk);

	if (ret) {

		dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");

		goto err_disable_vco;

		goto err_disable_oscin;

	}



	for (i = 0; i < info->num_channels; i++) {

		ret = lmk04832_register_clkout(lmk, i);

		if (ret) {

			dev_err(lmk->dev, "failed to register clk %d\n", i);

			goto err_disable_vco;

			goto err_disable_oscin;

		}

	}
@@ -1527,16 +1541,13 @@ static int lmk04832_probe(struct spi_device *spi) 
					  lmk->clk_data);

	if (ret) {

		dev_err(lmk->dev, "failed to add provider (%d)\n", ret);

		goto err_disable_vco;

		goto err_disable_oscin;

	}



	spi_set_drvdata(spi, lmk);



	return 0;



err_disable_vco:

	clk_disable_unprepare(lmk->vco.clk);



err_disable_oscin:

	clk_disable_unprepare(lmk->oscin);