Commit 960535d5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-6.6' of... 

Merge tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Add the PDM IPC clock for i.MX93
 - Add 519.75MHz frequency support for i.MX9 PLL
 - Simplify the .determine_rate() for GPR mux
 - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource
 - Add the audio mux clock to i.MX8
 - Fix the SPLL2 MULT range for PLLv4
 - Update the SPLL2 type in i.MX8ULP
 - Fix the SAI4 clock on i.MX8MP
 - Add silicon revision print for i.MX25 on clocks init
 - Drop the return value from __mx25_clocks_init
 - Fix the clock pauses on no-op set_rate for i.MX8M composite clock
 - Drop restrictions for PLL14xx and fix its max prediv value
 - Drop the 393216000 and 361267200 from PLL14xx rate table to allow
   glitch free switching

* tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
  clk: imx: pll14xx: align pdiv with reference manual
  clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
  clk: imx25: make __mx25_clocks_init return void
  clk: imx25: print silicon revision during init
  dt-bindings: clocks: imx8mp: make sai4 a dummy clock
  clk: imx8mp: fix sai4 clock
  clk: imx: imx8ulp: update SPLL2 type
  clk: imx: pllv4: Fix SPLL2 MULT range
  clk: imx: imx8: add audio clock mux driver
  dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
  clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
  clk: imx: clk-gpr-mux: Simplify .determine_rate()
  clk: imx: Add 519.75MHz frequency support for imx9 pll
  clk: imx93: Add PDM IPG clk
  dt-bindings: clock: imx93: Add PDM IPG clk
parents 06c2afb8 72d00e56

Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8 Audio Clock Mux



maintainers:

  - Shengjiu Wang <shengjiu.wang@nxp.com>



description: |

  NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP

  used to control Audio related clock on the SoC.



properties:

  compatible:

    enum:

      - fsl,imx8dxl-acm

      - fsl,imx8qm-acm

      - fsl,imx8qxp-acm



  reg:

    maxItems: 1



  power-domains:

    minItems: 13

    maxItems: 21



  '#clock-cells':

    const: 1

    description:

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h

      for the full list of i.MX8 ACM clock IDs.



  clocks:

    minItems: 13

    maxItems: 27



  clock-names:

    minItems: 13

    maxItems: 27



required:

  - compatible

  - reg

  - power-domains

  - '#clock-cells'

  - clocks

  - clock-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qxp-acm

    then:

      properties:

        power-domains:

          items:

            - description: power domain of IMX_SC_R_AUDIO_CLK_0

            - description: power domain of IMX_SC_R_AUDIO_CLK_1

            - description: power domain of IMX_SC_R_MCLK_OUT_0

            - description: power domain of IMX_SC_R_MCLK_OUT_1

            - description: power domain of IMX_SC_R_AUDIO_PLL_0

            - description: power domain of IMX_SC_R_AUDIO_PLL_1

            - description: power domain of IMX_SC_R_ASRC_0

            - description: power domain of IMX_SC_R_ASRC_1

            - description: power domain of IMX_SC_R_ESAI_0

            - description: power domain of IMX_SC_R_SAI_0

            - description: power domain of IMX_SC_R_SAI_1

            - description: power domain of IMX_SC_R_SAI_2

            - description: power domain of IMX_SC_R_SAI_3

            - description: power domain of IMX_SC_R_SAI_4

            - description: power domain of IMX_SC_R_SAI_5

            - description: power domain of IMX_SC_R_SPDIF_0

            - description: power domain of IMX_SC_R_MQS_0



        clocks:

          minItems: 18

          maxItems: 18



        clock-names:

          items:

            - const: aud_rec_clk0_lpcg_clk

            - const: aud_rec_clk1_lpcg_clk

            - const: aud_pll_div_clk0_lpcg_clk

            - const: aud_pll_div_clk1_lpcg_clk

            - const: ext_aud_mclk0

            - const: ext_aud_mclk1

            - const: esai0_rx_clk

            - const: esai0_rx_hf_clk

            - const: esai0_tx_clk

            - const: esai0_tx_hf_clk

            - const: spdif0_rx

            - const: sai0_rx_bclk

            - const: sai0_tx_bclk

            - const: sai1_rx_bclk

            - const: sai1_tx_bclk

            - const: sai2_rx_bclk

            - const: sai3_rx_bclk

            - const: sai4_rx_bclk



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qm-acm

    then:

      properties:

        power-domains:

          items:

            - description: power domain of IMX_SC_R_AUDIO_CLK_0

            - description: power domain of IMX_SC_R_AUDIO_CLK_1

            - description: power domain of IMX_SC_R_MCLK_OUT_0

            - description: power domain of IMX_SC_R_MCLK_OUT_1

            - description: power domain of IMX_SC_R_AUDIO_PLL_0

            - description: power domain of IMX_SC_R_AUDIO_PLL_1

            - description: power domain of IMX_SC_R_ASRC_0

            - description: power domain of IMX_SC_R_ASRC_1

            - description: power domain of IMX_SC_R_ESAI_0

            - description: power domain of IMX_SC_R_ESAI_1

            - description: power domain of IMX_SC_R_SAI_0

            - description: power domain of IMX_SC_R_SAI_1

            - description: power domain of IMX_SC_R_SAI_2

            - description: power domain of IMX_SC_R_SAI_3

            - description: power domain of IMX_SC_R_SAI_4

            - description: power domain of IMX_SC_R_SAI_5

            - description: power domain of IMX_SC_R_SAI_6

            - description: power domain of IMX_SC_R_SAI_7

            - description: power domain of IMX_SC_R_SPDIF_0

            - description: power domain of IMX_SC_R_SPDIF_1

            - description: power domain of IMX_SC_R_MQS_0



        clocks:

          minItems: 27

          maxItems: 27



        clock-names:

          items:

            - const: aud_rec_clk0_lpcg_clk

            - const: aud_rec_clk1_lpcg_clk

            - const: aud_pll_div_clk0_lpcg_clk

            - const: aud_pll_div_clk1_lpcg_clk

            - const: mlb_clk

            - const: hdmi_rx_mclk

            - const: ext_aud_mclk0

            - const: ext_aud_mclk1

            - const: esai0_rx_clk

            - const: esai0_rx_hf_clk

            - const: esai0_tx_clk

            - const: esai0_tx_hf_clk

            - const: esai1_rx_clk

            - const: esai1_rx_hf_clk

            - const: esai1_tx_clk

            - const: esai1_tx_hf_clk

            - const: spdif0_rx

            - const: spdif1_rx

            - const: sai0_rx_bclk

            - const: sai0_tx_bclk

            - const: sai1_rx_bclk

            - const: sai1_tx_bclk

            - const: sai2_rx_bclk

            - const: sai3_rx_bclk

            - const: sai4_rx_bclk

            - const: sai5_tx_bclk

            - const: sai6_rx_bclk



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8dxl-acm

    then:

      properties:

        power-domains:

          items:

            - description: power domain of IMX_SC_R_AUDIO_CLK_0

            - description: power domain of IMX_SC_R_AUDIO_CLK_1

            - description: power domain of IMX_SC_R_MCLK_OUT_0

            - description: power domain of IMX_SC_R_MCLK_OUT_1

            - description: power domain of IMX_SC_R_AUDIO_PLL_0

            - description: power domain of IMX_SC_R_AUDIO_PLL_1

            - description: power domain of IMX_SC_R_ASRC_0

            - description: power domain of IMX_SC_R_SAI_0

            - description: power domain of IMX_SC_R_SAI_1

            - description: power domain of IMX_SC_R_SAI_2

            - description: power domain of IMX_SC_R_SAI_3

            - description: power domain of IMX_SC_R_SPDIF_0

            - description: power domain of IMX_SC_R_MQS_0



        clocks:

          minItems: 13

          maxItems: 13



        clock-names:

          items:

            - const: aud_rec_clk0_lpcg_clk

            - const: aud_rec_clk1_lpcg_clk

            - const: aud_pll_div_clk0_lpcg_clk

            - const: aud_pll_div_clk1_lpcg_clk

            - const: ext_aud_mclk0

            - const: ext_aud_mclk1

            - const: spdif0_rx

            - const: sai0_rx_bclk

            - const: sai0_tx_bclk

            - const: sai1_rx_bclk

            - const: sai1_tx_bclk

            - const: sai2_rx_bclk

            - const: sai3_rx_bclk



additionalProperties: false



examples:

  # Clock Control Module node:

  - |

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    clock-controller@59e00000 {

        compatible = "fsl,imx8qxp-acm";

        reg = <0x59e00000 0x1d0000>;

        #clock-cells = <1>;

        power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,

                        <&pd IMX_SC_R_AUDIO_CLK_1>,

                        <&pd IMX_SC_R_MCLK_OUT_0>,

                        <&pd IMX_SC_R_MCLK_OUT_1>,

                        <&pd IMX_SC_R_AUDIO_PLL_0>,

                        <&pd IMX_SC_R_AUDIO_PLL_1>,

                        <&pd IMX_SC_R_ASRC_0>,

                        <&pd IMX_SC_R_ASRC_1>,

                        <&pd IMX_SC_R_ESAI_0>,

                        <&pd IMX_SC_R_SAI_0>,

                        <&pd IMX_SC_R_SAI_1>,

                        <&pd IMX_SC_R_SAI_2>,

                        <&pd IMX_SC_R_SAI_3>,

                        <&pd IMX_SC_R_SAI_4>,

                        <&pd IMX_SC_R_SAI_5>,

                        <&pd IMX_SC_R_SPDIF_0>,

                        <&pd IMX_SC_R_MQS_0>;

        clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,

                 <&aud_rec1_lpcg IMX_LPCG_CLK_0>,

                 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,

                 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,

                 <&clk_ext_aud_mclk0>,

                 <&clk_ext_aud_mclk1>,

                 <&clk_esai0_rx_clk>,

                 <&clk_esai0_rx_hf_clk>,

                 <&clk_esai0_tx_clk>,

                 <&clk_esai0_tx_hf_clk>,

                 <&clk_spdif0_rx>,

                 <&clk_sai0_rx_bclk>,

                 <&clk_sai0_tx_bclk>,

                 <&clk_sai1_rx_bclk>,

                 <&clk_sai1_tx_bclk>,

                 <&clk_sai2_rx_bclk>,

                 <&clk_sai3_rx_bclk>,

                 <&clk_sai4_rx_bclk>;

        clock-names = "aud_rec_clk0_lpcg_clk",

                      "aud_rec_clk1_lpcg_clk",

                      "aud_pll_div_clk0_lpcg_clk",

                      "aud_pll_div_clk1_lpcg_clk",

                      "ext_aud_mclk0",

                      "ext_aud_mclk1",

                      "esai0_rx_clk",

                      "esai0_rx_hf_clk",

                      "esai0_tx_clk",

                      "esai0_tx_hf_clk",

                      "spdif0_rx",

                      "sai0_rx_bclk",

                      "sai0_tx_bclk",

                      "sai1_rx_bclk",

                      "sai1_tx_bclk",

                      "sai2_rx_bclk",

                      "sai3_rx_bclk",

                      "sai4_rx_bclk";

    };

drivers/clk/imx/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -32,11 +32,12 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o 


obj-$(CONFIG_CLK_IMX93) += clk-imx93.o



obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o

obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o

clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \

				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \

				     clk-imx8dxl-rsrc.o

clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o

clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o



obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o

drivers/clk/imx/clk-composite-8m.c

+7 −5
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, 
	int prediv_value;

	int div_value;

	int ret;

	u32 val;

	u32 orig, val;



	ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,

						&prediv_value, &div_value);
@@ -106,12 +106,14 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, 


	spin_lock_irqsave(divider->lock, flags);



	val = readl(divider->reg);

	val &= ~((clk_div_mask(divider->width) << divider->shift) |

	orig = readl(divider->reg);

	val = orig & ~((clk_div_mask(divider->width) << divider->shift) |

		       (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));



	val |= (u32)(prediv_value  - 1) << divider->shift;

	val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;



	if (val != orig)

		writel(val, divider->reg);



	spin_unlock_irqrestore(divider->lock, flags);

drivers/clk/imx/clk-fracn-gppll.c

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { 
	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),

	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),

	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),

	PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),

	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),

	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),

	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),

drivers/clk/imx/clk-gpr-mux.c

+1 −7
Original line number Diff line number Diff line
@@ -65,16 +65,10 @@ static int imx_clk_gpr_mux_set_parent(struct clk_hw *hw, u8 index) 
	return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val);

}



static int imx_clk_gpr_mux_determine_rate(struct clk_hw *hw,

					 struct clk_rate_request *req)

{

	return clk_mux_determine_rate_flags(hw, req, 0);

}



static const struct clk_ops imx_clk_gpr_mux_ops = {

	.get_parent = imx_clk_gpr_mux_get_parent,

	.set_parent = imx_clk_gpr_mux_set_parent,

	.determine_rate = imx_clk_gpr_mux_determine_rate,

	.determine_rate = __clk_mux_determine_rate,

};



struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,