Commit 032bcf78 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and... 

Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next

 - Add Versa3 clk generator to support 48KHz playback/record with audio
   codec on RZ/G2L SMARC EVK
 - Introduce kstrdup_and_replace() and use it

* clk-versa:
  clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
  clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
  clk: versaclock3: Switch to use i2c_driver's probe callback
  clk: Add support for versa3 clock driver
  dt-bindings: clock: Add Renesas versa3 clock generator bindings

* clk-strdup:
  clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  lib/string_helpers: Add kstrdup_and_replace() helper

* clk-amlogic: (22 commits)
  dt-bindings: soc: amlogic: document System Control registers
  dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
  dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
  clk: meson: axg-audio: move bindings include to main driver
  clk: meson: meson8b: move bindings include to main driver
  clk: meson: a1: move bindings include to main driver
  clk: meson: eeclk: move bindings include to main driver
  clk: meson: aoclk: move bindings include to main driver
  dt-bindings: clk: axg-audio-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
  dt-bindings: clk: meson8b-clkc: expose all clock ids
  dt-bindings: clk: g12a-aoclkc: expose all clock ids
  dt-bindings: clk: g12a-clks: expose all clock ids
  dt-bindings: clk: axg-clkc: expose all clock ids
  dt-bindings: clk: gxbb-clkc: expose all clock ids
  clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
  ...

* clk-allwinner:
  clk: sunxi-ng: nkm: Prefer current parent rate
  clk: sunxi-ng: a64: select closest rate for pll-video0
  clk: sunxi-ng: div: Support finding closest rate
  clk: sunxi-ng: mux: Support finding closest rate
  clk: sunxi-ng: nkm: Support finding closest rate
  clk: sunxi-ng: nm: Support finding closest rate
  clk: sunxi-ng: Add helper function to find closest rate
  clk: sunxi-ng: Add feature to find closest rate
  clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
  clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
  clk: sunxi-ng: nkm: Use correct parameter name for parent HW
  clk: sunxi-ng: Modify mismatched function name
  clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()

* clk-rockchip:
  clk: rockchip: rv1126: Add PD_VO clock tree
  clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  clk: rockchip: rk3568: Add PLL rate for 101MHz
parents d10ebc7c fccd617f bb362d0e caf0dced 364a609d 438c61a7

Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt

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* Amlogic GXBB AO Clock and Reset Unit



The Amlogic GXBB AO clock controller generates and supplies clock to various

controllers within the Always-On part of the SoC.



Required Properties:



- compatible: value should be different for each SoC family as :

	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"

	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"

	- GXM (S912) : "amlogic,meson-gxm-aoclkc"

	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"

	- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"

	followed by the common "amlogic,meson-gx-aoclkc"

- clocks: list of clock phandle, one for each entry clock-names.

- clock-names: should contain the following:

  * "xtal"     : the platform xtal

  * "mpeg-clk" : the main clock controller mother clock (aka clk81)

  * "ext-32k-0"  : external 32kHz reference #0 if any (optional)

  * "ext-32k-1"  : external 32kHz reference #1 if any (optional - gx only)

  * "ext-32k-2"  : external 32kHz reference #2 if any (optional - gx only)



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be

used in device tree sources.



- #reset-cells: should be 1.



Each reset is assigned an identifier and client nodes can use this identifier

to specify the reset which they consume. All available resets are defined as

preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be

used in device tree sources.



Parent node should have the following properties :

- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"

- reg: base address and size of the AO system control register space.



Example: AO Clock controller node:



ao_sysctrl: sys-ctrl@0 {

	compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";

	reg =  <0x0 0x0 0x0 0x100>;



	clkc_AO: clock-controller {

		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";

		#clock-cells = <1>;

		#reset-cells = <1>;

		clocks = <&xtal>, <&clkc CLKID_CLK81>;

		clock-names = "xtal", "mpeg-clk";

	};



Example: UART controller node that consumes the clock and reset generated

  by the clock controller:



	uart_AO: serial@4c0 {

		compatible = "amlogic,meson-uart";

		reg = <0x4c0 0x14>;

		interrupts = <0 90 1>;

		clocks = <&clkc_AO CLKID_AO_UART1>;

		resets = <&clkc_AO RESET_AO_UART1>;

	};

Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic Always-On Clock Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - amlogic,meson-gxbb-aoclkc

              - amlogic,meson-gxl-aoclkc

              - amlogic,meson-gxm-aoclkc

              - amlogic,meson-axg-aoclkc

          - const: amlogic,meson-gx-aoclkc

      - enum:

          - amlogic,meson-axg-aoclkc

          - amlogic,meson-g12a-aoclkc



  clocks:

    minItems: 2

    maxItems: 5



  clock-names:

    minItems: 2

    items:

      - const: xtal

      - const: mpeg-clk

      - const: ext-32k-0

      - const: ext-32k-1

      - const: ext-32k-2



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



allOf:

  - if:

      properties:

        compatible:

          enum:

            - amlogic,meson-g12a-aoclkc



    then:

      properties:

        clocks:

          minItems: 2

          maxItems: 3



        clock-names:

          minItems: 2

          maxItems: 3



  - if:

      properties:

        compatible:

          enum:

            - amlogic,meson-gxl-aoclkc

            - amlogic,meson-gxm-aoclkc

            - amlogic,meson-axg-aoclkc



    then:

      properties:

        clocks:

          maxItems: 2



        clock-names:

          maxItems: 2



additionalProperties: false

Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt

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* Amlogic GXBB Clock and Reset Unit



The Amlogic GXBB clock controller generates and supplies clock to various

controllers within the SoC.



Required Properties:



- compatible: should be:

		"amlogic,gxbb-clkc" for GXBB SoC,

		"amlogic,gxl-clkc" for GXL and GXM SoC,

		"amlogic,axg-clkc" for AXG SoC.

		"amlogic,g12a-clkc" for G12A SoC.

		"amlogic,g12b-clkc" for G12B SoC.

		"amlogic,sm1-clkc" for SM1 SoC.

- clocks : list of clock phandle, one for each entry clock-names.

- clock-names : should contain the following:

  * "xtal": the platform xtal



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be

used in device tree sources.



Parent node should have the following properties :

- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or

              "amlogic,meson-axg-hhi-sysctrl"

- reg: base address and size of the HHI system control register space.



Example: Clock controller node:



sysctrl: system-controller@0 {

	compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";

	reg = <0 0 0 0x400>;



	clkc: clock-controller {

		#clock-cells = <1>;

		compatible = "amlogic,gxbb-clkc";

		clocks = <&xtal>;

		clock-names = "xtal";

	};

};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart_AO: serial@c81004c0 {

		compatible = "amlogic,meson-uart";

		reg = <0xc81004c0 0x14>;

		interrupts = <0 90 1>;

		clocks = <&clkc CLKID_CLK81>;

	};

Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic Clock Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>



properties:

  compatible:

    enum:

      - amlogic,gxbb-clkc

      - amlogic,gxl-clkc

      - amlogic,axg-clkc

      - amlogic,g12a-clkc

      - amlogic,g12b-clkc

      - amlogic,sm1-clkc



  clocks:

    maxItems: 1



  clock-names:

    const: xtal



  '#clock-cells':

    const: 1



required:

  - compatible

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false

Documentation/devicetree/bindings/clock/renesas,5p35023.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator



maintainers:

  - Biju Das <biju.das.jz@bp.renesas.com>



description: |

  The 5P35023 is a VersaClock programmable clock generator and

  is designed for low-power, consumer, and high-performance PCI

  express applications. The 5P35023 device is a three PLL

  architecture design, and each PLL is individually programmable

  and allowing for up to 6 unique frequency outputs.



  An internal OTP memory allows the user to store the configuration

  in the device. After power up, the user can change the device register

  settings through the I2C interface when I2C mode is selected.



  The driver can read a full register map from the DT, and will use that

  register map to initialize the attached part (via I2C) when the system

  boots. Any configuration not supported by the common clock framework

  must be done via the full register map, including optimized settings.



  Link to datasheet:

  https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator



properties:

  compatible:

    enum:

      - renesas,5p35023



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    maxItems: 1



  renesas,settings:

    description: Optional, complete register map of the device.

      Optimized settings for the device must be provided in full

      and are written during initialization.

    $ref: /schemas/types.yaml#/definitions/uint8-array

    maxItems: 37



required:

  - compatible

  - reg

  - '#clock-cells'

  - clocks



additionalProperties: false



examples:

  - |

    i2c {

        #address-cells = <1>;

        #size-cells = <0>;



        versa3: clock-generator@68 {

            compatible = "renesas,5p35023";

            reg = <0x68>;

            #clock-cells = <1>;



            clocks = <&x1_x2>;



            renesas,settings = [

                80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf

                00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6

                80 b0 45 c4 95

            ];



            assigned-clocks = <&versa3 0>, <&versa3 1>,

                              <&versa3 2>, <&versa3 3>,

                              <&versa3 4>, <&versa3 5>;

            assigned-clock-rates = <12288000>, <25000000>,

                                   <12000000>, <11289600>,

                                   <11289600>, <24000000>;

        };

    };