Commit d10ebc7c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and... 

Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next

 - Remove OXNAS clk driver

* clk-bindings:
  dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
  dt-bindings: clock: xlnx,versal-clk: drop select:false
  dt-bindings: clock: versal: Add versal-net compatible string
  dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
  dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding

* clk-starfive:
  reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
  clk: starfive: Simplify .determine_rate()
  clk: starfive: Add StarFive JH7110 Video-Output clock driver
  clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
  clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
  clk: starfive: jh7110-sys: Add PLL clocks source from DTS
  clk: starfive: Add StarFive JH7110 PLL clock driver
  dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
  dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
  dt-bindings: soc: starfive: Add StarFive syscon module
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator

* clk-rm:
  dt-bindings: clk: oxnas: remove obsolete bindings
  clk: oxnas: remove obsolete clock driver

* clk-renesas:
  clk: renesas: rcar-gen3: Add ADG clocks
  clk: renesas: r8a77965: Add 3DGE and ZG support
  clk: renesas: r8a7796: Add 3DGE and ZG support
  clk: renesas: r8a7795: Add 3DGE and ZG support
  clk: renesas: emev2: Remove obsolete clkdev registration
  clk: renesas: r9a07g043: Add MTU3a clock and reset entry
  clk: renesas: rzg2l: Simplify .determine_rate()
  clk: renesas: r9a09g011: Add CSI related clocks
  clk: renesas: r8a774b1: Add 3DGE and ZG support
  clk: renesas: r8a774e1: Add 3DGE and ZG support
  clk: renesas: r8a774a1: Add 3DGE and ZG support
  clk: renesas: rcar-gen3: Add support for ZG clock

* clk-cleanup:
  clk: mvebu: Convert to devm_platform_ioremap_resource()
  clk: nuvoton: Convert to devm_platform_ioremap_resource()
  clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
  clk: ti: Use devm_platform_get_and_ioremap_resource()
  clk: mediatek: Convert to devm_platform_ioremap_resource()
  clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
  clk: gemini: Convert to devm_platform_ioremap_resource()
  clk: fsl-sai: Convert to devm_platform_ioremap_resource()
  clk: bm1880: Convert to devm_platform_ioremap_resource()
  clk: axm5516: Convert to devm_platform_ioremap_resource()
  clk: actions: Convert to devm_platform_ioremap_resource()
  clk: cdce925: Remove redundant of_match_ptr()
  drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()
  clk: Explicitly include correct DT includes
parents 03d4a100 0e2b2a76 096110aa 772b4559 0a26c3f8

Documentation/devicetree/bindings/clock/oxnas,stdclk.txt

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Oxford Semiconductor OXNAS SoC Family Standard Clocks

================================================



Please also refer to clock-bindings.txt in this directory for common clock

bindings usage.



Required properties:

- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"

	      For OX820, should be "oxsemi,ox820-stdclk"

- #clock-cells: 1, see below



Parent node should have the following properties :

- compatible: For OX810SE, should be

		"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"

	      For OX820, should be

		"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"



example:



sys: sys-ctrl@000000 {

	compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";

	reg = <0x000000 0x100000>;



	stdclk: stdclk {

		compatible = "oxsemi,ox810se-stdclk";

		#clock-cells = <1>;

	};

};

Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-ispcrg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: ISP Top core

      - description: ISP Top Axi

      - description: NOC ISP Bus

      - description: external DVP



  clock-names:

    items:

      - const: isp_top_core

      - const: isp_top_axi

      - const: noc_bus_isp_axi

      - const: dvp_clk



  resets:

    items:

      - description: ISP Top core

      - description: ISP Top Axi

      - description: NOC ISP Bus



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



  power-domains:

    maxItems: 1

    description:

      ISP domain power



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - '#clock-cells'

  - '#reset-cells'

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>

    #include <dt-bindings/power/starfive,jh7110-pmu.h>

    #include <dt-bindings/reset/starfive,jh7110-crg.h>



    ispcrg: clock-controller@19810000 {

        compatible = "starfive,jh7110-ispcrg";

        reg = <0x19810000 0x10000>;

        clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,

                 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,

                 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,

                 <&dvp_clk>;

        clock-names = "isp_top_core", "isp_top_axi",

                      "noc_bus_isp_axi", "dvp_clk";

        resets = <&syscrg JH7110_SYSRST_ISP_TOP>,

                 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,

                 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        power-domains = <&pwrc JH7110_PD_ISP>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 PLL Clock Generator



description:

  These PLLs are high speed, low jitter frequency synthesizers in the JH7110.

  Each PLL works in integer mode or fraction mode, with configuration

  registers in the sys syscon. So the PLLs node should be a child of

  SYS-SYSCON node.

  The formula for calculating frequency is

  Fvco = Fref * (NI + NF) / M / Q1



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-pll



  clocks:

    maxItems: 1

    description: Main Oscillator (24 MHz)



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller {

      compatible = "starfive,jh7110-pll";

      clocks = <&osc>;

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 System-Top-Group Clock and Reset Generator



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-stgcrg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Main Oscillator (24 MHz)

      - description: HIFI4 core

      - description: STG AXI/AHB

      - description: USB (125 MHz)

      - description: CPU Bus

      - description: HIFI4 Axi

      - description: NOC STG Bus

      - description: APB Bus



  clock-names:

    items:

      - const: osc

      - const: hifi4_core

      - const: stg_axiahb

      - const: usb_125m

      - const: cpu_bus

      - const: hifi4_axi

      - const: nocstg_bus

      - const: apb_bus



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>



    stgcrg: clock-controller@10230000 {

        compatible = "starfive,jh7110-stgcrg";

        reg = <0x10230000 0x10000>;

        clocks = <&osc>,

                 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,

                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,

                 <&syscrg JH7110_SYSCLK_USB_125M>,

                 <&syscrg JH7110_SYSCLK_CPU_BUS>,

                 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,

                 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,

                 <&syscrg JH7110_SYSCLK_APB_BUS>;

        clock-names = "osc", "hifi4_core",

                      "stg_axiahb", "usb_125m",

                      "cpu_bus", "hifi4_axi",

                      "nocstg_bus", "apb_bus";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

+16 −2
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ properties: 
          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock

          - description: PLL0

          - description: PLL1

          - description: PLL2



      - items:

          - description: Main Oscillator (24 MHz)
@@ -38,6 +41,9 @@ properties: 
          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock

          - description: PLL0

          - description: PLL1

          - description: PLL2



  clock-names:

    oneOf:
@@ -52,6 +58,9 @@ properties: 
          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext

          - const: pll0_out

          - const: pll1_out

          - const: pll2_out



      - items:

          - const: osc
@@ -63,6 +72,9 @@ properties: 
          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext

          - const: pll0_out

          - const: pll1_out

          - const: pll2_out



  '#clock-cells':

    const: 1
@@ -93,12 +105,14 @@ examples: 
                 <&gmac1_rgmii_rxin>,

                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

                 <&tdm_ext>, <&mclk_ext>;

                 <&tdm_ext>, <&mclk_ext>,

                 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;

        clock-names = "osc", "gmac1_rmii_refin",

                      "gmac1_rgmii_rxin",

                      "i2stx_bclk_ext", "i2stx_lrck_ext",

                      "i2srx_bclk_ext", "i2srx_lrck_ext",

                      "tdm_ext", "mclk_ext";

                      "tdm_ext", "mclk_ext",

                      "pll0_out", "pll1_out", "pll2_out";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };