Commit 03d4a100 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Stephen Boyd
Browse files

dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml 



Convert the xlnx,zynqmp-clk.txt to yaml.
versal-clk.yaml already exists that's why ZynqMP is converted and
merged.

Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20230802043557.26478-1-shubhrajyoti.datta@amd.com


Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 172044e3

Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml

+71 −9
Original line number Diff line number Diff line
@@ -17,7 +17,9 @@ description: | 
properties:

  compatible:

    oneOf:

      - const: xlnx,versal-clk

      - enum:

          - xlnx,versal-clk

          - xlnx,zynqmp-clk

      - items:

          - enum:

              - xlnx,versal-net-clk
@@ -29,6 +31,32 @@ properties: 
  clocks:

    description: List of clock specifiers which are external input

      clocks to the given clock controller.

    minItems: 3

    maxItems: 8



  clock-names:

    minItems: 3

    maxItems: 8



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names



additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - xlnx,versal-clk



    then:

      properties:

        clocks:

          items:

            - description: reference clock

            - description: alternate reference clock
@@ -40,13 +68,38 @@ properties: 
            - const: alt_ref

            - const: pl_alt_ref



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names

  - if:

      properties:

        compatible:

          contains:

            enum:

              - xlnx,zynqmp-clk



additionalProperties: false

    then:

      properties:

        clocks:

          minItems: 5

          items:

            - description: PS reference clock

            - description: reference clock for video system

            - description: alternative PS reference clock

            - description: auxiliary reference clock

            - description: transceiver reference clock

            - description: (E)MIO clock source  (Optional clock)

            - description: GEM emio clock  (Optional clock)

            - description: Watchdog external clock (Optional clock)



        clock-names:

          minItems: 5

          items:

            - const: pss_ref_clk

            - const: video_clk

            - const: pss_alt_ref_clk

            - const: aux_ref_clk

            - const: gt_crx_ref_clk

            - pattern: "^mio_clk[00-77]+.*$"

            - pattern: "gem[0-3]+_emio_clk.*$"

            - pattern: "swdt[0-1]+_ext_clk.*$"



examples:

  - |
@@ -62,4 +115,13 @@ examples: 
        };

      };

    };



    clock-controller {

        #clock-cells = <1>;

        compatible = "xlnx,zynqmp-clk";

        clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,

                 <&aux_ref_clk>, <&gt_crx_ref_clk>;

        clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",

                      "aux_ref_clk", "gt_crx_ref_clk";

    };

...

Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt

deleted100644 → 0
+0 −63
Original line number Diff line number Diff line 
--------------------------------------------------------------------------

Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using

Zynq MPSoC firmware interface

--------------------------------------------------------------------------

The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

tree. It reads required input clock frequencies from the devicetree and acts

as clock provider for all clock consumers of PS clocks.



See clock_bindings.txt for more information on the generic clock bindings.



Required properties:

 - #clock-cells:	Must be 1

 - compatible:		Must contain:	"xlnx,zynqmp-clk"

 - clocks:		List of clock specifiers which are external input

			clocks to the given clock controller. Please refer

			the next section to find the input clocks for a

			given controller.

 - clock-names:		List of clock names which are exteral input clocks

			to the given clock controller. Please refer to the

			clock bindings for more details.



Input clocks for zynqmp Ultrascale+ clock controller:



The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock

inputs. These required clock inputs are:

 - pss_ref_clk (PS reference clock)

 - video_clk (reference clock for video system )

 - pss_alt_ref_clk (alternative PS reference clock)

 - aux_ref_clk

 - gt_crx_ref_clk (transceiver reference clock)



The following strings are optional parameters to the 'clock-names' property in

order to provide an optional (E)MIO clock source:

 - swdt0_ext_clk

 - swdt1_ext_clk

 - gem0_emio_clk

 - gem1_emio_clk

 - gem2_emio_clk

 - gem3_emio_clk

 - mio_clk_XX		# with XX = 00..77

 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51





Output clocks are registered based on clock information received

from firmware. Output clocks indexes are mentioned in

include/dt-bindings/clock/xlnx-zynqmp-clk.h.



-------

Example

-------



firmware {

	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";

		method = "smc";

		zynqmp_clk: clock-controller {

			#clock-cells = <1>;

			compatible = "xlnx,zynqmp-clk";

			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

		};

	};

};