Commit 26d74926 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/microchip' 

- Fix DED and SEC interrupt bit offsets so interrupt handlers work
  correctly (Daire McNamara)

- Make driver buildable as a module (Daire McNamara)

- Reorganize register #defines to align with hardware docs (Daire McNamara)

- Tweak register accessors to simplify callers (Daire McNamara)

- Refactor interrupt initialisation (Daire McNamara)

- Read FPGA MSI configuration parameters from hardware instead of
  hard-coding them (Daire McNamara)

- Re-partition code between probe() and init() (Daire McNamara)

* pci/controller/microchip:
  PCI: microchip: Re-partition code between probe() and init()
  PCI: microchip: Gather MSI information from hardware config registers
  PCI: microchip: Clean up initialisation of interrupts
  PCI: microchip: Enable event handlers to access bridge and control pointers
  PCI: microchip: Align register, offset, and mask names with HW docs
  PCI: microchip: Enable building driver as a module
  PCI: microchip: Correct the DED and SEC interrupt bit offsets
parents aa5a239c bac406c3

drivers/pci/controller/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -217,7 +217,7 @@ config PCIE_MT7621 
	  This selects a driver for the MediaTek MT7621 PCIe Controller.



config PCIE_MICROCHIP_HOST

	bool "Microchip AXI PCIe controller"

	tristate "Microchip AXI PCIe controller"

	depends on PCI_MSI && OF

	select PCI_HOST_COMMON

	help

drivers/pci/controller/pcie-microchip-host.c

+232 −161
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 * Author: Daire McNamara <daire.mcnamara@microchip.com>

 */



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>
@@ -20,8 +21,7 @@ 
#include "../pci.h"



/* Number of MSI IRQs */

#define MC_NUM_MSI_IRQS				32

#define MC_NUM_MSI_IRQS_CODED			5

#define MC_MAX_NUM_MSI_IRQS			32



/* PCIe Bridge Phy and Controller Phy offsets */

#define MC_PCIE1_BRIDGE_ADDR			0x00008000u
@@ -30,65 +30,11 @@ 
#define MC_PCIE_BRIDGE_ADDR			(MC_PCIE1_BRIDGE_ADDR)

#define MC_PCIE_CTRL_ADDR			(MC_PCIE1_CTRL_ADDR)



/* PCIe Controller Phy Regs */

#define SEC_ERROR_CNT				0x20

#define DED_ERROR_CNT				0x24

#define SEC_ERROR_INT				0x28

#define  SEC_ERROR_INT_TX_RAM_SEC_ERR_INT	GENMASK(3, 0)

#define  SEC_ERROR_INT_RX_RAM_SEC_ERR_INT	GENMASK(7, 4)

#define  SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT	GENMASK(11, 8)

#define  SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT	GENMASK(15, 12)

#define  NUM_SEC_ERROR_INTS			(4)

#define SEC_ERROR_INT_MASK			0x2c

#define DED_ERROR_INT				0x30

#define  DED_ERROR_INT_TX_RAM_DED_ERR_INT	GENMASK(3, 0)

#define  DED_ERROR_INT_RX_RAM_DED_ERR_INT	GENMASK(7, 4)

#define  DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT	GENMASK(11, 8)

#define  DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT	GENMASK(15, 12)

#define  NUM_DED_ERROR_INTS			(4)

#define DED_ERROR_INT_MASK			0x34

#define ECC_CONTROL				0x38

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_0		BIT(0)

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_1		BIT(1)

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_2		BIT(2)

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_3		BIT(3)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_0		BIT(4)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_1		BIT(5)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_2		BIT(6)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_3		BIT(7)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0	BIT(8)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1	BIT(9)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2	BIT(10)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3	BIT(11)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0	BIT(12)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1	BIT(13)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2	BIT(14)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3	BIT(15)

#define  ECC_CONTROL_TX_RAM_ECC_BYPASS		BIT(24)

#define  ECC_CONTROL_RX_RAM_ECC_BYPASS		BIT(25)

#define  ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS	BIT(26)

#define  ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS	BIT(27)

#define LTSSM_STATE				0x5c

#define  LTSSM_L0_STATE				0x10

#define PCIE_EVENT_INT				0x14c

#define  PCIE_EVENT_INT_L2_EXIT_INT		BIT(0)

#define  PCIE_EVENT_INT_HOTRST_EXIT_INT		BIT(1)

#define  PCIE_EVENT_INT_DLUP_EXIT_INT		BIT(2)

#define  PCIE_EVENT_INT_MASK			GENMASK(2, 0)

#define  PCIE_EVENT_INT_L2_EXIT_INT_MASK	BIT(16)

#define  PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK	BIT(17)

#define  PCIE_EVENT_INT_DLUP_EXIT_INT_MASK	BIT(18)

#define  PCIE_EVENT_INT_ENB_MASK		GENMASK(18, 16)

#define  PCIE_EVENT_INT_ENB_SHIFT		16

#define  NUM_PCIE_EVENTS			(3)



/* PCIe Bridge Phy Regs */

#define PCIE_PCI_IDS_DW1			0x9c



/* PCIe Config space MSI capability structure */

#define MC_MSI_CAP_CTRL_OFFSET			0xe0u

#define  MC_MSI_MAX_Q_AVAIL			(MC_NUM_MSI_IRQS_CODED << 1)

#define  MC_MSI_Q_SIZE				(MC_NUM_MSI_IRQS_CODED << 4)

#define PCIE_PCI_IRQ_DW0			0xa8

#define  MSIX_CAP_MASK				BIT(31)

#define  NUM_MSI_MSGS_MASK			GENMASK(6, 4)

#define  NUM_MSI_MSGS_SHIFT			4



#define IMASK_LOCAL				0x180

#define  DMA_END_ENGINE_0_MASK			0x00000000u
@@ -137,7 +83,7 @@ 
#define ISTATUS_LOCAL				0x184

#define IMASK_HOST				0x188

#define ISTATUS_HOST				0x18c

#define MSI_ADDR				0x190

#define IMSI_ADDR				0x190

#define ISTATUS_MSI				0x194



/* PCIe Master table init defines */
@@ -162,17 +108,73 @@ 


#define ATR_ENTRY_SIZE				32



/* PCIe Controller Phy Regs */

#define SEC_ERROR_EVENT_CNT			0x20

#define DED_ERROR_EVENT_CNT			0x24

#define SEC_ERROR_INT				0x28

#define  SEC_ERROR_INT_TX_RAM_SEC_ERR_INT	GENMASK(3, 0)

#define  SEC_ERROR_INT_RX_RAM_SEC_ERR_INT	GENMASK(7, 4)

#define  SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT	GENMASK(11, 8)

#define  SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT	GENMASK(15, 12)

#define  SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT	GENMASK(15, 0)

#define  NUM_SEC_ERROR_INTS			(4)

#define SEC_ERROR_INT_MASK			0x2c

#define DED_ERROR_INT				0x30

#define  DED_ERROR_INT_TX_RAM_DED_ERR_INT	GENMASK(3, 0)

#define  DED_ERROR_INT_RX_RAM_DED_ERR_INT	GENMASK(7, 4)

#define  DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT	GENMASK(11, 8)

#define  DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT	GENMASK(15, 12)

#define  DED_ERROR_INT_ALL_RAM_DED_ERR_INT	GENMASK(15, 0)

#define  NUM_DED_ERROR_INTS			(4)

#define DED_ERROR_INT_MASK			0x34

#define ECC_CONTROL				0x38

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_0		BIT(0)

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_1		BIT(1)

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_2		BIT(2)

#define  ECC_CONTROL_TX_RAM_INJ_ERROR_3		BIT(3)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_0		BIT(4)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_1		BIT(5)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_2		BIT(6)

#define  ECC_CONTROL_RX_RAM_INJ_ERROR_3		BIT(7)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0	BIT(8)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1	BIT(9)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2	BIT(10)

#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3	BIT(11)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0	BIT(12)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1	BIT(13)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2	BIT(14)

#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3	BIT(15)

#define  ECC_CONTROL_TX_RAM_ECC_BYPASS		BIT(24)

#define  ECC_CONTROL_RX_RAM_ECC_BYPASS		BIT(25)

#define  ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS	BIT(26)

#define  ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS	BIT(27)

#define PCIE_EVENT_INT				0x14c

#define  PCIE_EVENT_INT_L2_EXIT_INT		BIT(0)

#define  PCIE_EVENT_INT_HOTRST_EXIT_INT		BIT(1)

#define  PCIE_EVENT_INT_DLUP_EXIT_INT		BIT(2)

#define  PCIE_EVENT_INT_MASK			GENMASK(2, 0)

#define  PCIE_EVENT_INT_L2_EXIT_INT_MASK	BIT(16)

#define  PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK	BIT(17)

#define  PCIE_EVENT_INT_DLUP_EXIT_INT_MASK	BIT(18)

#define  PCIE_EVENT_INT_ENB_MASK		GENMASK(18, 16)

#define  PCIE_EVENT_INT_ENB_SHIFT		16

#define  NUM_PCIE_EVENTS			(3)



/* PCIe Config space MSI capability structure */

#define MC_MSI_CAP_CTRL_OFFSET			0xe0u



/* Events */

#define EVENT_PCIE_L2_EXIT			0

#define EVENT_PCIE_HOTRST_EXIT			1

#define EVENT_PCIE_DLUP_EXIT			2

#define EVENT_SEC_TX_RAM_SEC_ERR		3

#define EVENT_SEC_RX_RAM_SEC_ERR		4

#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR		5

#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR		6

#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR		5

#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR		6

#define EVENT_DED_TX_RAM_DED_ERR		7

#define EVENT_DED_RX_RAM_DED_ERR		8

#define EVENT_DED_AXI2PCIE_RAM_DED_ERR		9

#define EVENT_DED_PCIE2AXI_RAM_DED_ERR		10

#define EVENT_DED_PCIE2AXI_RAM_DED_ERR		9

#define EVENT_DED_AXI2PCIE_RAM_DED_ERR		10

#define EVENT_LOCAL_DMA_END_ENGINE_0		11

#define EVENT_LOCAL_DMA_END_ENGINE_1		12

#define EVENT_LOCAL_DMA_ERROR_ENGINE_0		13
@@ -259,7 +261,7 @@ struct mc_msi { 
	struct irq_domain *dev_domain;

	u32 num_vectors;

	u64 vector_phy;

	DECLARE_BITMAP(used, MC_NUM_MSI_IRQS);

	DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS);

};



struct mc_pcie {
@@ -382,25 +384,29 @@ static struct { 


static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };



static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base)

static struct mc_pcie *port;



static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam)

{

	struct mc_msi *msi = &port->msi;

	u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET;

	u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS);

	u16 reg;

	u8 queue_size;



	msg_ctrl |= PCI_MSI_FLAGS_ENABLE;

	msg_ctrl &= ~PCI_MSI_FLAGS_QMASK;

	msg_ctrl |= MC_MSI_MAX_Q_AVAIL;

	msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;

	msg_ctrl |= MC_MSI_Q_SIZE;

	msg_ctrl |= PCI_MSI_FLAGS_64BIT;

	/* Fixup MSI enable flag */

	reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);

	reg |= PCI_MSI_FLAGS_ENABLE;

	writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);



	writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);

	/* Fixup PCI MSI queue flags */

	queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg);

	reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size);

	writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);



	/* Fixup MSI addr fields */

	writel_relaxed(lower_32_bits(msi->vector_phy),

		       base + cap_offset + PCI_MSI_ADDRESS_LO);

		       ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO);

	writel_relaxed(upper_32_bits(msi->vector_phy),

		       base + cap_offset + PCI_MSI_ADDRESS_HI);

		       ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI);

}



static void mc_handle_msi(struct irq_desc *desc)
@@ -473,10 +479,7 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 
{

	struct mc_pcie *port = domain->host_data;

	struct mc_msi *msi = &port->msi;

	void __iomem *bridge_base_addr =

		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	unsigned long bit;

	u32 val;



	mutex_lock(&msi->lock);

	bit = find_first_zero_bit(msi->used, msi->num_vectors);
@@ -490,11 +493,6 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 
	irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip,

			    domain->host_data, handle_edge_irq, NULL, NULL);



	/* Enable MSI interrupts */

	val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);

	val |= PM_MSI_INT_MSI_MASK;

	writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);



	mutex_unlock(&msi->lock);



	return 0;
@@ -656,9 +654,10 @@ static inline u32 reg_to_event(u32 reg, struct event_map field) 
	return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;

}



static u32 pcie_events(void __iomem *addr)

static u32 pcie_events(struct mc_pcie *port)

{

	u32 reg = readl_relaxed(addr);

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;

	u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT);

	u32 val = 0;

	int i;
@@ -668,9 +667,10 @@ static u32 pcie_events(void __iomem *addr) 
	return val;

}



static u32 sec_errors(void __iomem *addr)

static u32 sec_errors(struct mc_pcie *port)

{

	u32 reg = readl_relaxed(addr);

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;

	u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT);

	u32 val = 0;

	int i;
@@ -680,9 +680,10 @@ static u32 sec_errors(void __iomem *addr) 
	return val;

}



static u32 ded_errors(void __iomem *addr)

static u32 ded_errors(struct mc_pcie *port)

{

	u32 reg = readl_relaxed(addr);

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;

	u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT);

	u32 val = 0;

	int i;
@@ -692,9 +693,10 @@ static u32 ded_errors(void __iomem *addr) 
	return val;

}



static u32 local_events(void __iomem *addr)

static u32 local_events(struct mc_pcie *port)

{

	u32 reg = readl_relaxed(addr);

	void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);

	u32 val = 0;

	int i;
@@ -706,15 +708,12 @@ static u32 local_events(void __iomem *addr) 


static u32 get_events(struct mc_pcie *port)

{

	void __iomem *bridge_base_addr =

		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;

	u32 events = 0;



	events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT);

	events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT);

	events |= ded_errors(ctrl_base_addr + DED_ERROR_INT);

	events |= local_events(bridge_base_addr + ISTATUS_LOCAL);

	events |= pcie_events(port);

	events |= sec_errors(port);

	events |= ded_errors(port);

	events |= local_events(port);



	return events;

}
@@ -987,39 +986,73 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, 
	return 0;

}



static int mc_platform_init(struct pci_config_window *cfg)

static inline void mc_clear_secs(struct mc_pcie *port)

{

	struct device *dev = cfg->parent;

	struct platform_device *pdev = to_platform_device(dev);

	struct mc_pcie *port;

	void __iomem *bridge_base_addr;

	void __iomem *ctrl_base_addr;

	int ret;

	int irq;

	int i, intx_irq, msi_irq, event_irq;

	u32 val;

	int err;

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;



	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);

	if (!port)

		return -ENOMEM;

	port->dev = dev;

	writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +

		       SEC_ERROR_INT);

	writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);

}



	ret = mc_pcie_init_clks(dev);

	if (ret) {

		dev_err(dev, "failed to get clock resources, error %d\n", ret);

		return -ENODEV;

static inline void mc_clear_deds(struct mc_pcie *port)

{

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;



	writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +

		       DED_ERROR_INT);

	writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);

}



	port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);

	if (IS_ERR(port->axi_base_addr))

		return PTR_ERR(port->axi_base_addr);

static void mc_disable_interrupts(struct mc_pcie *port)

{

	void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;

	u32 val;



	bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;

	/* Ensure ECC bypass is enabled */

	val = ECC_CONTROL_TX_RAM_ECC_BYPASS |

	      ECC_CONTROL_RX_RAM_ECC_BYPASS |

	      ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS |

	      ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS;

	writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);



	/* Disable SEC errors and clear any outstanding */

	writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr +

		       SEC_ERROR_INT_MASK);

	mc_clear_secs(port);



	/* Disable DED errors and clear any outstanding */

	writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr +

		       DED_ERROR_INT_MASK);

	mc_clear_deds(port);



	/* Disable local interrupts and clear any outstanding */

	writel_relaxed(0, bridge_base_addr + IMASK_LOCAL);

	writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL);

	writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI);



	/* Disable PCIe events and clear any outstanding */

	val = PCIE_EVENT_INT_L2_EXIT_INT |

	      PCIE_EVENT_INT_HOTRST_EXIT_INT |

	      PCIE_EVENT_INT_DLUP_EXIT_INT |

	      PCIE_EVENT_INT_L2_EXIT_INT_MASK |

	      PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK |

	      PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;

	writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);



	/* Disable host interrupts and clear any outstanding */

	writel_relaxed(0, bridge_base_addr + IMASK_HOST);

	writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);

}



static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port)

{

	struct device *dev = &pdev->dev;

	int irq;

	int i, intx_irq, msi_irq, event_irq;

	int ret;



	port->msi.vector_phy = MSI_ADDR;

	port->msi.num_vectors = MC_NUM_MSI_IRQS;

	ret = mc_pcie_init_irq_domains(port);

	if (ret) {

		dev_err(dev, "failed creating IRQ domains\n");
@@ -1037,11 +1070,11 @@ static int mc_platform_init(struct pci_config_window *cfg) 
			return -ENXIO;

		}



		err = devm_request_irq(dev, event_irq, mc_event_handler,

		ret = devm_request_irq(dev, event_irq, mc_event_handler,

				       0, event_cause[i].sym, port);

		if (err) {

		if (ret) {

			dev_err(dev, "failed to request IRQ %d\n", event_irq);

			return err;

			return ret;

		}

	}
@@ -1066,44 +1099,81 @@ static int mc_platform_init(struct pci_config_window *cfg) 
	/* Plug the main event chained handler */

	irq_set_chained_handler_and_data(irq, mc_handle_event, port);



	/* Hardware doesn't setup MSI by default */

	return 0;

}



static int mc_platform_init(struct pci_config_window *cfg)

{

	struct device *dev = cfg->parent;

	struct platform_device *pdev = to_platform_device(dev);

	void __iomem *bridge_base_addr =

		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	int ret;



	/* Configure address translation table 0 for PCIe config space */

	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,

			     cfg->res.start,

			     resource_size(&cfg->res));



	/* Need some fixups in config space */

	mc_pcie_enable_msi(port, cfg->win);



	val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);

	val |= PM_MSI_INT_INTX_MASK;

	writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);

	/* Configure non-config space outbound ranges */

	ret = mc_pcie_setup_windows(pdev, port);

	if (ret)

		return ret;



	writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);

	/* Address translation is up; safe to enable interrupts */

	ret = mc_init_interrupts(pdev, port);

	if (ret)

		return ret;



	val = PCIE_EVENT_INT_L2_EXIT_INT |

	      PCIE_EVENT_INT_HOTRST_EXIT_INT |

	      PCIE_EVENT_INT_DLUP_EXIT_INT;

	writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);

	return 0;

}



	val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT |

	      SEC_ERROR_INT_RX_RAM_SEC_ERR_INT |

	      SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT |

	      SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;

	writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);

	writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);

	writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);



	val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |

	      DED_ERROR_INT_RX_RAM_DED_ERR_INT |

	      DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT |

	      DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;

	writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);

	writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);

	writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);

static int mc_host_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	void __iomem *bridge_base_addr;

	int ret;

	u32 val;



	writel_relaxed(0, bridge_base_addr + IMASK_HOST);

	writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);

	if (!port)

		return -ENOMEM;



	port->dev = dev;



	port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);

	if (IS_ERR(port->axi_base_addr))

		return PTR_ERR(port->axi_base_addr);



	mc_disable_interrupts(port);



	bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;



	/* Allow enabling MSI by disabling MSI-X */

	val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);

	val &= ~MSIX_CAP_MASK;

	writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);



	/* Pick num vectors from bitfile programmed onto FPGA fabric */

	val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);

	val &= NUM_MSI_MSGS_MASK;

	val >>= NUM_MSI_MSGS_SHIFT;



	port->msi.num_vectors = 1 << val;



	/* Configure Address Translation Table 0 for PCIe config space */

	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,

			     cfg->res.start, resource_size(&cfg->res));

	/* Pick vector address from design */

	port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);



	ret = mc_pcie_init_clks(dev);

	if (ret) {

		dev_err(dev, "failed to get clock resources, error %d\n", ret);

		return -ENODEV;

	}



	return mc_pcie_setup_windows(pdev, port);

	return pci_host_common_probe(pdev);

}



static const struct pci_ecam_ops mc_ecam_ops = {
@@ -1126,7 +1196,7 @@ static const struct of_device_id mc_pcie_of_match[] = { 
MODULE_DEVICE_TABLE(of, mc_pcie_of_match);



static struct platform_driver mc_pcie_driver = {

	.probe = pci_host_common_probe,

	.probe = mc_host_probe,

	.driver = {

		.name = "microchip-pcie",

		.of_match_table = mc_pcie_of_match,
@@ -1135,5 +1205,6 @@ static struct platform_driver mc_pcie_driver = { 
};



builtin_platform_driver(mc_pcie_driver);

MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("Microchip PCIe host controller driver");

MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");