Commit aa5a239c authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/layerscape' 

- Add support for link-down notification so the endpoint driver can process
  LINK_DOWN events (Frank Li)

- Save Link Capabilities during probe so they can be restored when handling
  a link-up event, since the controller loses the Link Width and Link Speed
  values during reset (Xiaowei Bao)

* pci/controller/layerscape:
  PCI: layerscape: Add workaround for lost link capabilities during reset
  PCI: layerscape: Add support for link-down notification
parents d4218e2a 17cf8661

drivers/pci/controller/dwc/pci-layerscape-ep.c

+20 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ struct ls_pcie_ep { 
	struct pci_epc_features		*ls_epc;

	const struct ls_pcie_ep_drvdata *drvdata;

	int				irq;

	u32				lnkcap;

	bool				big_endian;

};
@@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
	struct ls_pcie_ep *pcie = dev_id;

	struct dw_pcie *pci = pcie->pci;

	u32 val, cfg;

	u8 offset;



	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);

	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
@@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
		return IRQ_NONE;



	if (val & PEX_PF0_PME_MES_DR_LUD) {



		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);



		/*

		 * The values of the Maximum Link Width and Supported Link

		 * Speed from the Link Capabilities Register will be lost

		 * during link down or hot reset. Restore initial value

		 * that configured by the Reset Configuration Word (RCW).

		 */

		dw_pcie_dbi_ro_wr_en(pci);

		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);

		dw_pcie_dbi_ro_wr_dis(pci);



		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);

		cfg |= PEX_PF0_CFG_READY;

		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
@@ -89,6 +104,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
		dev_dbg(pci->dev, "Link up\n");

	} else if (val & PEX_PF0_PME_MES_DR_LDD) {

		dev_dbg(pci->dev, "Link down\n");

		pci_epc_linkdown(pci->ep.epc);

	} else if (val & PEX_PF0_PME_MES_DR_HRD) {

		dev_dbg(pci->dev, "Hot reset\n");

	}
@@ -215,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) 
	struct ls_pcie_ep *pcie;

	struct pci_epc_features *ls_epc;

	struct resource *dbi_base;

	u8 offset;

	int ret;



	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
@@ -251,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) 


	platform_set_drvdata(pdev, pcie);



	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);



	ret = dw_pcie_ep_init(&pci->ep);

	if (ret)

		return ret;