Commit bac406c3 authored by Daire McNamara's avatar Daire McNamara Committed by Lorenzo Pieralisi
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PCI: microchip: Re-partition code between probe() and init() 

Continuing to use pci_host_common_probe() for the PCIe Root Complex on
PolarFire SoC is leading to an extremely large _init() function and some
unnatural code flow. Re-partition the code so that some tasks are done
in a _probe() routine, which calls pci_host_common_probe() and then use
a much smaller _init() function, mainly to enable interrupts after
address translation tables are set up.

Link: https://lore.kernel.org/r/20230728131401.1615724-8-daire.mcnamara@microchip.com


Signed-off-by: default avatarDaire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 1abb7228

drivers/pci/controller/pcie-microchip-host.c

+38 −20
Original line number Diff line number Diff line
@@ -384,6 +384,8 @@ static struct { 


static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };



static struct mc_pcie *port;



static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam)

{

	struct mc_msi *msi = &port->msi;
@@ -1104,7 +1106,34 @@ static int mc_platform_init(struct pci_config_window *cfg) 
{

	struct device *dev = cfg->parent;

	struct platform_device *pdev = to_platform_device(dev);

	struct mc_pcie *port;

	void __iomem *bridge_base_addr =

		port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;

	int ret;



	/* Configure address translation table 0 for PCIe config space */

	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,

			     cfg->res.start,

			     resource_size(&cfg->res));



	/* Need some fixups in config space */

	mc_pcie_enable_msi(port, cfg->win);



	/* Configure non-config space outbound ranges */

	ret = mc_pcie_setup_windows(pdev, port);

	if (ret)

		return ret;



	/* Address translation is up; safe to enable interrupts */

	ret = mc_init_interrupts(pdev, port);

	if (ret)

		return ret;



	return 0;

}



static int mc_host_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	void __iomem *bridge_base_addr;

	int ret;

	u32 val;
@@ -1112,13 +1141,8 @@ static int mc_platform_init(struct pci_config_window *cfg) 
	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);

	if (!port)

		return -ENOMEM;

	port->dev = dev;



	ret = mc_pcie_init_clks(dev);

	if (ret) {

		dev_err(dev, "failed to get clock resources, error %d\n", ret);

		return -ENODEV;

	}

	port->dev = dev;



	port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);

	if (IS_ERR(port->axi_base_addr))
@@ -1133,9 +1157,6 @@ static int mc_platform_init(struct pci_config_window *cfg) 
	val &= ~MSIX_CAP_MASK;

	writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0);



	/* Hardware doesn't setup MSI by default */

	mc_pcie_enable_msi(port, cfg->win);



	/* Pick num vectors from bitfile programmed onto FPGA fabric */

	val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);

	val &= NUM_MSI_MSGS_MASK;
@@ -1146,16 +1167,13 @@ static int mc_platform_init(struct pci_config_window *cfg) 
	/* Pick vector address from design */

	port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR);



	/* Configure Address Translation Table 0 for PCIe config space */

	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,

			     cfg->res.start, resource_size(&cfg->res));



	ret = mc_pcie_setup_windows(pdev, port);

	if (ret)

		return ret;

	ret = mc_pcie_init_clks(dev);

	if (ret) {

		dev_err(dev, "failed to get clock resources, error %d\n", ret);

		return -ENODEV;

	}



	/* Address translation is up; safe to enable interrupts */

	return mc_init_interrupts(pdev, port);

	return pci_host_common_probe(pdev);

}



static const struct pci_ecam_ops mc_ecam_ops = {
@@ -1178,7 +1196,7 @@ static const struct of_device_id mc_pcie_of_match[] = { 
MODULE_DEVICE_TABLE(of, mc_pcie_of_match);



static struct platform_driver mc_pcie_driver = {

	.probe = pci_host_common_probe,

	.probe = mc_host_probe,

	.driver = {

		.name = "microchip-pcie",

		.of_match_table = mc_pcie_of_match,