!30 Intel SPR: powercap: intel_rapl: support new layout of Psys PowerLimit Register layout

Merge pull request from @juntianlinux:

On Sapphire Rapids, the layout of the Psys domain Power Limit Register
is different from from what it was before.
Enhance the code to support the new Psys PL register layout.

Test:
Psys only supported on some SKU and upstream team has done test on this.
no change for upstream patch.

Config:
n/a

Link: https://gitee.com/openeuler/kernel/pulls/30

 

From: @juntianlinux 
Reviewed-by: Zheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com>