powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR

mainline inclusion
mainline-5.17
commit 931da6a0
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BED0



Intel-SIG: commit 931da6a0 powercap: intel_rapl: support new layout
of Psys PowerLimit Register on SPR.
Backport for SPR RAPL Psys support.

-------------------------------------

On Sapphire Rapids, the layout of the Psys domain Power Limit Register
is different from from what it was before.

Enhance the code to support the new Psys PL register layout.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reported-and-tested-by: Alkattan Dana <dana.alkattan@intel.com>
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: yingbao jia <yingbao.jia@intel.com>
Signed-off-by: Jun Tian <jun.j.tian@intel.com>