- Nov 14, 2017
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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Vinod Koul authored
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- Nov 08, 2017
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Adam Wallis authored
Commit adfa543e ("dmatest: don't use set_freezable_with_signal()") introduced a bug (that is in fact documented by the patch commit text) that leaves behind a dangling pointer. Since the done_wait structure is allocated on the stack, future invocations to the DMATEST can produce undesirable results (e.g., corrupted spinlocks). Ideally, this would be cleaned up in the thread handler, but at the very least, the kernel is left in a very precarious scenario that can lead to some long debug sessions when the crash comes later. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197605 Signed-off-by:
Adam Wallis <awallis@codeaurora.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Vinod Koul authored
This reverts commit 847449f2 : ("dmaengine: rcar-dmac: use TCRB instead of TCR for residue") as it breaks small serial console. Reported-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Pierre-Yves MORDRET authored
If source and destination bus width differs pack/unpack MDMA feature has to be activated for alignment. This pack/unpack feature implies to have both source/destination address and buffer length aligned on bus width. Fixes: a4ffb13c ("dmaengine: Add STM32 MDMA driver") Signed-off-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Vinod Koul authored
Since commit 3cab1e71 ("lib/vsprintf: refactor duplicate code to special_hex_number()") %pad doesn't need 0x prefix so drop that. Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Vinod Koul authored
Since commit 3cab1e71 ("lib/vsprintf: refactor duplicate code to special_hex_number()") %pad doesn't need 0x prefix so drop that. Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Nov 02, 2017
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Andy Shevchenko authored
As discussed at ELCE 2017 there is little to anticipate from me in the future with regard to the driver, and since I have many things to keep an eye on, I would like to step down to simple designated reviewer. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 31, 2017
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Romain Perier authored
The PCI pool API is deprecated. This commit replaces the PCI pool old API by the appropriate function with the DMA pool API. Signed-off-by:
Romain Perier <romain.perier@collabora.com> Acked-by:
Peter Senna Tschudin <peter.senna@collabora.com> Tested-by:
Peter Senna Tschudin <peter.senna@collabora.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 23, 2017
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Anup Patel authored
By default, we build Broadcom SBA RAID driver as loadable module for iProc SOCs so that kernel image is little smaller and we load SBA RAID driver only when required. Signed-off-by:
Anup Patel <anup.patel@broadcom.com> Reviewed-by:
Scott Branden <scott.branden@broadcom.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Anup Patel authored
This patch makes the comment header of Broadcom SBA RAID driver similar to the GPL comment header used across Broadcom driver sources. Signed-off-by:
Anup Patel <anup.patel@broadcom.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Anup Patel authored
Each mailbox channel used by Broadcom SBA RAID driver is a separate HW ring. Currently, Broadcom SBA RAID driver creates one DMA channel using one or more mailbox channels. When we are using more than one mailbox channels for a DMA channel, the sba_request are distributed evenly among multiple mailbox channels which results in sba_request being completed out-of-order. The above described out-of-order completion of sba_request breaks the dma_async_is_complete() API because it assumes DMA cookies are completed in orderly fashion. To ensure correct behaviour of dma_async_is_complete() API, this patch updates Broadcom SBA RAID driver to use only single mailbox channel. If additional mailbox channels are specified in DT then those will be ignored. Signed-off-by:
Anup Patel <anup.patel@broadcom.com> Reviewed-by:
Ray Jui <ray.jui@broadcom.com> Reviewed-by:
Scott Branden <scott.branden@broadcom.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Anup Patel authored
As-per documentation in driver/dma/dmaengine.h, the dma_cookie_complete() API should be called with lock held. This patch ensures that Broadcom SBA RAID driver calls the dma_cookie_complete() API with reqs_lock held. Signed-off-by:
Anup Patel <anup.patel@broadcom.com> Reviewed-by:
Ray Jui <ray.jui@broadcom.com> Reviewed-by:
Scott Branden <scott.branden@broadcom.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 20, 2017
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Alexander Kochetkov authored
If two concurrent threads call pl330_get_desc() when DMAC descriptor pool is empty it is possible that allocation for one of threads will fail with message: kernel: dma-pl330 20078000.dma-controller: pl330_get_desc:2469 ALERT! Here how that can happen. Thread A calls pl330_get_desc() to get descriptor. If DMAC descriptor pool is empty pl330_get_desc() allocates new descriptor on shared pool using add_desc() and then get newly allocated descriptor using pluck_desc(). At the same time thread B calls pluck_desc() and take newly allocated descriptor. In that case descriptor allocation for thread A will fail. Using on-stack pool for new descriptor allow avoid the issue described. The patch modify pl330_get_desc() to use on-stack pool for allocation new descriptors. Signed-off-by:
Alexander Kochetkov <al.kochet@gmail.com> Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Hiroyuki Yokoyama authored
SYS/RT/Audio DMAC includes independent data buffers for reading and writing. Therefore, the read transfer counter and write transfer counter have different values. TCR indicates read counter, and TCRB indicates write counter. The relationship is like below. TCR TCRB [SOURCE] -> [DMAC] -> [SINK] In the MEM_TO_DEV direction, what really matters is how much data has been written to the device. If the DMA is interrupted between read and write, then, the data doesn't end up in the destination, so shouldn't be counted. TCRB is thus the register we should use in this cases. In the DEV_TO_MEM direction, the situation is more complex. Both the read and write side are important. What matters from a data consumer point of view is how much data has been written to memory. On the other hand, if the transfer is interrupted between read and write, we'll end up losing data. It can also be important to report. In the MEM_TO_MEM direction, what matters is of course how much data has been written to memory from data consumer point of view. Here, because read and write have independent data buffers, it will take a while for TCR and TCRB to become equal. Thus we should check TCRB in this case, too. Thus, all cases we should check TCRB instead of TCR. Without this patch, Sound Capture has noise after PluseAudio support (= 07b7acb5 ("ASoC: rsnd: update pointer more accurate")), because the recorder will use wrong residue counter which indicates transferred from sound device, but in reality the data was not yet put to memory and recorder will record it. Signed-off-by:
Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> [Kuninori: added detail information in log] Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 16, 2017
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Ed Blake authored
Add runtime PM support to disable the clock when the h/w is not in use. The existing clock_prepare_enable is removed from probe() as the clock is no longer permanently enabled. Signed-off-by:
Ed Blake <ed.blake@sondrel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Ed Blake authored
Add suspend / resume handling using suspend_late and resume_early, and check that all channels are idle before suspending. DMA drivers should use suspend_late / resume_early to ensure that all DMA client devices are suspended before the DMA device itself, and that client devices are resumed after the DMA device. This avoids suspending the DMA device while transactions are still active. It is the responsibility of client drivers to terminate all DMA transactions in their suspend handlers, so there should be no active transactions by the time suspend_late is called. There's no need to save and restore registers for MDC during suspend / resume, as all transactions will be terminated as a result of the suspend, and all required registers are programmed anyway at the start of any new transactions following resume. Signed-off-by:
Ed Blake <ed.blake@sondrel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 13, 2017
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Geert Uytterhoeven authored
Use the of_device_get_match_data() helper instead of open coding. Note that when used with DT, there's always a valid match. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 12, 2017
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Colin Ian King authored
hwdesc is being initialized to desc->hwdesc but this is never read as hwdesc is overwritten in a for-loop. Remove the redundant initialization and move the declaration of hwdesc into the for-loop. Cleans up clang warning: Value stored to 'hwdesc' during its initialization is never read Signed-off-by:
Colin Ian King <colin.king@canonical.com> Acked-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Arnd Bergmann authored
Without CONFIG_OF we get a build warning: warning: (STM32_MDMA) selects DMA_OF which has unmet direct dependencies (DMADEVICES && OF) This adds a dependency on CONFIG_OF. Since this means we no longer need to select 'DMA_OF', I'm dropping that line as well. Fixes: a4ffb13c ("dmaengine: Add STM32 MDMA driver") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Oct 08, 2017
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Vinod Koul authored
Pointer print was using explict cast and printing as %x which causes below warn on some arch's so print using %p format specfier. Reported-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Biju Das authored
This patch adds support for r8a7743/5 SoCs. The Renesas RZ/G1[ME] (R8A7743/5) usbdmac engine is identical to the R-Car Gen2 family. No driver change is needed due to the fallback compatible value "renesas,r8a7743-usb-dmac". Adding the SoC-specific compatible values here has two purposes: 1. Document which SoCs have this hardware module, 2. Allow checkpatch to validate compatible values. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Signed-off-by:
Chris Paterson <chris.paterson2@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Dan Carpenter authored
devm_ioremap_resource() doesn't return NULL, it returns error pointers. Fixes: df7e762d ("dmaengine: Add STM32 DMAMUX driver") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Acked-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Pierre-Yves MORDRET authored
This patch adds the driver for the STM32 MDMA controller. Master Direct memory access (MDMA) is used in order to provide high-speed data transfer between memory and memory or between peripherals and memory. MDMA controller provides a master AXI interface for main memory and peripheral registers access (system access port) and a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2). It offers up to 64 channels, each dedicated to managing memory access requests from one of the DMA stream memory buffer or other peripherals (w/ integrated FIFO). Signed-off-by:
M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Pierre-Yves MORDRET authored
This patch adds documentation of device tree bindings for the STM32 MDMA controller. Signed-off-by:
M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Sep 27, 2017
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Russell King authored
Add DMA filters for the sa11x0 DMA channels. This will allow us to migrate away from directly using the DMA filter function in drivers. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Pierre-Yves MORDRET authored
STM32 DMA controller has to exposed its number of request line to be addressed via STM32 DMAMUX. Signed-off-by:
M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Pierre-Yves MORDRET authored
This patch implements the STM32 DMAMUX driver. The DMAMUX request multiplexer allows routing a DMA request line between the peripherals and the DMA controllers of the product. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. The DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals Signed-off-by:
M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Pierre-Yves MORDRET authored
This patch adds the documentation of device tree bindings for the STM32 DMAMUX. Signed-off-by:
M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by:
Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- Sep 25, 2017
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Sricharan R authored
The bam dmaengine has a circular FIFO to which we add hw descriptors that describes the transaction. The FIFO has space for about 4096 hw descriptors. Currently we add one descriptor and wait for it to complete with interrupt and then add the next pending descriptor. In this way, the FIFO is underutilized since only one descriptor is processed at a time, although there is space in FIFO for the BAM to process more. Instead keep adding descriptors to FIFO till its full, that allows BAM to continue to work on the next descriptor immediately after signalling completion interrupt for the previous descriptor. Also when the client has not set the DMA_PREP_INTERRUPT for a descriptor, then do not configure BAM to trigger a interrupt upon completion of that descriptor. This way we get a interrupt only for the descriptor for which DMA_PREP_INTERRUPT was requested and there signal completion of all the previous completed descriptors. So we still do callbacks for all requested descriptors, but just that the number of interrupts are reduced. CURRENT: ------ ------- --------------- |DES 0| |DESC 1| |DESC 2 + INT | ------ ------- --------------- | | | | | | INTERRUPT: (INT) (INT) (INT) CALLBACK: (CB) (CB) (CB) MTD_SPEEDTEST READ PAGE: 3560 KiB/s MTD_SPEEDTEST WRITE PAGE: 2664 KiB/s IOZONE READ: 2456 KB/s IOZONE WRITE: 1230 KB/s bam dma interrupts (after tests): 96508 CHANGE: ------ ------- ------------- |DES 0| |DESC 1 |DESC 2 + INT | ------ ------- -------------- | | (INT) (CB for 0, 1, 2) MTD_SPEEDTEST READ PAGE: 3860 KiB/s MTD_SPEEDTEST WRITE PAGE: 2837 KiB/s IOZONE READ: 2677 KB/s IOZONE WRITE: 1308 KB/s bam dma interrupts (after tests): 58806 Signed-off-by:
Sricharan R <sricharan@codeaurora.org> Reviewed-by:
Andy Gross <andy.gross@linaro.org> Tested-by:
Abhishek Sahu <absahu@codeaurora.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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